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Category: Main/Reference/Papers
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Automated risk elimination by formally critiquing verification plan and design documentation
Description: There are always risks of missing bugs in functional verification. Using a formal analysis
engine with very high capacity, we are able to eliminate such risks by formally proving
that it is safe not to run a given class of test cases. This risk elimination solution works
well with all verification flows because it only requires the waveform of a transaction and
some user interaction (indicating what will be well verified about this transaction) in
addition to the Verilog RTL. If it finds any test case in the class that can show any
surprise, it generates a Verilog testbench to use in a normal simulation/debugging
environment.
Added on: 11-Feb-2006 Hits: 474
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Cliff Cummings' Verilog & SystemVerilog Papers
Description: Freely downloadable Verilog & SystemVerilog design, synthesis and verification papers, including many award-winning papers, from recognized Verilog & SystemVerilog Expert, Cliff Cummings. Cliff has participated on, and contributed to every IEEE and Accellera Verilog, Verilog Synthesis and SystemVerilog Standards Group.
Added on: 12-Oct-2005 Hits: 759
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State Machine Coverage Using Specman
Description: by Jacob Joseph
Added on: 16-Nov-2004 Hits: 3011
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