| Login | | Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. | |
| Who's Online | There are currently, 36 guest(s) and 1 member(s) that are online.
You are Anonymous user. You can register for free by clicking here | |
 | |
| Most Popular - Top 25 | Show Top: [ 10 - 25 - 50 | 1% - 5% - 10% ]
| VMK: Generic Makefile generator for VHDL models
Description: A tool that peruses VHDL source code and figures out the compilation dependencies. It then generates a Makefile to compile the model in the correct order and minimize the recompilation necessary to maintain the VHDL model.
Completely tool-indenpendent. Can be used on ANY VHDL simulator.
Open source, licensed under Apache V2.0
Added on: 08-May-2007 Hits: 4232
Rate this Site
Category: Freeware/Tools
On-line Specman and e tutorial
Description: An overview of the e language
Added on: 01-Sep-2004 Hits: 3113
Rate this Site
Category: Freeware/Training
State Machine Coverage Using Specman
Description: by Jacob Joseph
Added on: 16-Nov-2004 Hits: 3028
Rate this Site
Category: Reference/Papers
Quick Reference Cards from Verifica
Description: Looking for a useful Quick Reference Card for Specman, Vera, Verilog or VHDL? It's available -- free -- in the Verifica Library.
Added on: 27-Dec-2003 Hits: 2736
Rate this Site
Category: Freeware/Training
Design Verification with e
Description: Written for both experienced and new users, Design Verification with e gives you a broad coverage of e. It stresses the practical verification perspective of e rather than emphasizing only its language aspects.
Added on: 27-Jan-2004 Hits: 2720
Rate this Site
Category: Reference/Books
Writing Testbenches: Functional Verification of HDL Models
Description: How to write testbenches using VHDL, Verilog, e or OpenVera.
Added on: 30-Nov-2003 Hits: 2567
Rate this Site
Category: Reference/Books
Specman verification blog
Description: A blog about everything HVL - including tips, bugs, coding techniques, personal experiences and personal traumas - with special emphasis on Specman-e and SystemVerilog for verification
Added on: 18-Feb-2006 Hits: 2552
Rate this Site
Category: Freeware/Training
Design And Reuse, The Web's System-On-Chip Design Resource
Description: D&R provides a global collaboration network for sharing design resources in the electronics SoC industry.
Added on: 31-Mar-2004 Hits: 2530
Rate this Site
Category: Freeware/IP
FPGA Central: FPGA Events, Forums, IP, Vendors, News, Webcast
Description: FPGA Central is created to provide a central place for FPGA Vendors & Users to share experiences and information about FPGA Design, Development, Verification, Validation, Process, Tools & Products.
Added on: 21-Sep-2007 Hits: 2512
Rate this Site
Category: Reference/Communities
Specman Yahoo! Group
Description: Yahoo! group for Specman users
Added on: 14-Dec-2003 Hits: 2448
Rate this Site
Category: Reference/Communities
Assertion-Based Design, Second Edition
Description: Text focuses on assertion-based design, showing how to specify assertions, create and adopt a methodology that supports assertion-based design, and what to do with the assertions and methodology once you have them. Discusses multiple forms of assertion specification, such as Accellera Open Verification Library (OVL).
Added on: 26-Aug-2004 Hits: 2437
Rate this Site
Category: Reference/Books
The Verifica Library
Description: We've created a selective collection of papers, references and other information to help you tackle your challenging verification and design tasks. Each library item includes an opinionated review of its more noteworthy insights so you can tap into its value quickly. Check it out.
Added on: 27-Dec-2003 Hits: 2384
Rate this Site
Category: Reference/Reference
Principles of Functional Verification
Description: Guide to understanding and managing the verification process to reach goals of predictable flow, efficient use of resources, and a successful project outcome. Includes an assessment of the time and risk trade-offs inherent in any verification process, how to plan and manage the verification portion of projects, and more.
Added on: 13-Feb-2004 Hits: 2361
Rate this Site
Category: Reference/Books
Professional Verification
Description: by Paul Wilcox
A guide to advanced functional verification in the nanometer era.
Added on: 09-Jun-2004 Hits: 2279
Rate this Site
Category: Reference/Books
Principles of Verifiable RTL Design
Description: Explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. Reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer.
Added on: 14-Dec-2003 Hits: 2181
Rate this Site
Category: Reference/Books
Functional Verification Coverage Measurement and Analysis
Description: by Andrew Piziali
Addresses means of quantitatively assess the progress of functional verification.
Added on: 09-Jun-2004 Hits: 2090
Rate this Site
Category: Reference/Books
Veripool
Description: Free, open-source tools for Verilog and SystemC
Added on: 19-Jul-2004 Hits: 2063
Rate this Site
Category: Freeware/Tools
PSL Quick Reference Guide for VHDL
Description: PSL Quick Reference Guide for VHDL
Added on: 24-Sep-2004 Hits: 2023
Rate this Site
Category: Freeware/Training
Dave Whipp's ASIC Design Verification Pages
Description: Personal pages of Dave Whipp: contains papers and notes on verification issues; plus links to other DV-related pages.
Added on: 06-Jan-2004 Hits: 1959
Rate this Site
Category: Reference/Individuals
VhdlCohen Publishing
Description: PSL and books,
Links to models and
links to other useful sites
Added on: 26-Aug-2004 Hits: 1955
Rate this Site
Category: Business/Business
Introduction to Formal Hardware Verification
Description: Presents an almost complete overview of techniques for hardware verification. Covers all approaches used in existing tools; binary and word-level decision diagrams, symbolic methods for equivalence checking, and temporal logic model checking, and introduces the use of higher-order logic theorem proving for verifying circuit correctness.
Added on: 20-Dec-2003 Hits: 1929
Rate this Site
Category: Reference/Books
Digital Systems Testing & Testable Design
Description: Considered a definitive text in this area, the book includes in-depth discussions of the following topics:
Test generation,
Fault modeling for classic and new technologies,
Simulation,
Fault simulation,
Design for testability,
Built-in self-test Diagnosis
Added on: 14-Dec-2003 Hits: 1893
Rate this Site
Category: Reference/Books
IP/SoC 2004
Description: IP/SOC 2004 (IP Based SoC Design) will be the 13th edition of the Working conference on hot topics in the design world, focusing for the past 4 years on IP based SoC design and hold in the well known Silicon and Alliance Nanometer Valley in the French Alps.
Added on: 31-Mar-2004 Hits: 1842
Rate this Site
Category: Technology/Conferences
Co-Verification of Hardware and Software for ARM SoC Design
Description: The first book written on HW/SW co-verification. The book
provides unique, in depth information about how co-verification really works, how to be successful using it, and the pitfalls to avoid. The book also contains an added bonus: it covers important information about developing and verifying SoC designs using ARM microprocessor cores.
Added on: 27-Aug-2004 Hits: 1806
Rate this Site
Category: Reference/Books
Model Checking
Description: Provides a comprehensive presentation of the theory and practice of model checking. Includes basic as well as state-of-the-art techniques, algorithms, and tools
Added on: 14-Dec-2003 Hits: 1800
Rate this Site
Category: Reference/Books
|
|
|
| | |
