| Login | | Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. | |
| Who's Online | There are currently, 39 guest(s) and 0 member(s) that are online.
You are Anonymous user. You can register for free by clicking here | |
 | |
|
Verification Guild: Forums |
|
| View previous topic :: View next topic |
| Author |
Message |
dmcnam
Newbie
Joined: Dec 15, 2004
Posts: 2
|
 Posted: Wed Dec 15, 2004 7:40 am Post subject: VHDL: Connecting IO's together within the same module |
 |
|
Hi all,
I have VHDL question that maybe somebody could help me with.
If you have two ports of types INOUT on an entity. How, within that architecture can you tie them together?
Note: I don't wan't to use a port map to tie them together.
Any suggestions would be appreciated.
Thanks,
Damien |
|
| Back to top |
|
 |
vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1237
Location: Los Angeles, CA
|
| Posted: Wed Dec 15, 2004 5:57 pm Post subject: |
|
|
| Quote: | If you have two ports of types INOUT on an entity. How, within that architecture can you tie them together?
Note: I don't wan't to use a port map to tie them together.
|
The best way is to create a shell as shown below.
| Code: |
library ieee;
use ieee.std_logic_1164.all;
entity E is
port (
a : inout std_logic;
b : inout std_logic);
end entity E;
library ieee;
use ieee.std_logic_1164.all;
entity Etop is
port (
c : inout std_logic);
end entity Etop;
-------------------------------------------------------------------------------
architecture top1 of Etop is
signal c : std_logic;
begin -- architecture top1
E_i: entity work.E
port map (
a => c, -- [inout std_logic]
b => c); -- [inout std_logic]
end architecture top1;
|
You cannot do within an architecture
c <=a;
c <= b;
I have at my site a model of a vhdl birectional switch, but there are restrictions, and it is not synthesisable.
Ben Cohen
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
|
| Back to top |
|
|
vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1237
Location: Los Angeles, CA
|
| Posted: Wed Dec 15, 2004 11:02 pm Post subject: |
|
|
Errata,
| Code: | architecture top1 of Etop is
-- signal c : std_logic; -- Delete this line
begin -- architecture top1
E_i: entity work.E
port map (
a => c, -- [inout std_logic]
b => c); -- [inout std_logic]
end architecture top1; |
.. some rust on my vhdl is beginning to show 
Ben
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
|
| Back to top |
|
|
dmcnam
Newbie
Joined: Dec 15, 2004
Posts: 2
|
| Posted: Thu Dec 16, 2004 4:19 am Post subject: |
|
|
Thanks for the tip. 
Damien |
|
| Back to top |
|
|
|
|
You can post new topics in this forum
You can reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
|
| |
|
|
Forum FAQ
Search
Usergroups
Profile
Digest
Log in
