cycle accurate model of RISC CPU

stevenyytan · Newbie Joined: Nov 05, 2004 Posts: 1

hi, I have finished a processor by VHDL and implemented it into FPGA. and now I want to verify the system timing. thus we need a cycle accurate model of system. because I did not write this model before and knew few about it, could you tell me where I find a simple cycle accurate model of a RISC CPU? or give me some suggestion to write it.

thanks

FaultFinder · Newbie Joined: Oct 19, 2004 Posts: 3

Hi Steven

I know of a company in Japan which has complete tool set for generating cycle accurate C models. You can either write one from scratch or convert an existing Verilog/VHDL model to plain C. With their integration tool you can even co-simulate HDL and cycle accurate C models.

http://www.adac.co.jp/eng/products/edatools/