Verification jobs: Is PSL or SVA knowledge a requirement?

vhdlcohen

From a curiosity viewpoint, I did a search at careerbuilder.com on keywords "PSL verilog vhdl", "SystemVerilog" and the search produced NO results.
A search on " verilog vhdl verification" produced interesting results. Below are some of job requirements, but in summary, it is interesting to me that those companies creating those postings overall seem to have never heard of a verification language, and seem to seek engineers with the traditional design definition, design and verification methodologies. For design definition, the job qualities are "good writing skill", and for verification "knowledge of testbench". Whatever happened to PSL / SystemVerilog Assertions / static verification?

I must be missing something here. Are employers not embracing this new ABV technology? Are emplyoyers seeking to do internal training, thus hiring people who are not necessarily into that technology? Are vendors / trade jounals doing a good job at educating this new technology supported by new languages?

SAHO · Senior Joined: Oct 16, 2004 Posts: 24

Ben:

I believe that PSL/System Verilog is yet becoming a mainstream part of verification job as most task are still done in HDL environment with some HVLs.

For INTEL, they are looking for people with Verilog, VHDL, and Specman skills to do verification. No mention of SystemVerilog and PSL.

For us (a networking player), we are beginning to look at some formal course in PSL before getting tool evaluations from EDA vendors that supporting PSL methodology along with HDL. The earliest date for our pilot project is some time early next year. Tool cost is always a CONCERN; as currently PSL are offered for premium high-end (expensive) products. Few PSL products for engineers using Microsoft Windows based environment as most Windows-desktop products are marketed as low cost andacceptable performance. I certainly would like to see more support from EDA vendors for Windows platform.

I did remember that John Cooley did a survey on interest in adopting assertion based verification; as far as I could remember, the response is not that encouraging.

I do agree with your observation that EDA vendors need to do even a better job at promoting PSL/System Verilog. My guess is that there is still a large proportion of companies that are NOT exposed to these methodologies. Books on PSL/System Verilog are extremely few.

SAHO