Why replace VHDL testbenches with SystemC testbenches ?

SAHO · Senior Joined: Oct 16, 2004 Posts: 24

Salute to all verification experts:

I am responsible for crafting system level verification environment for my company's networking products using FPGAs. The testbench environment is coded in VHDL using BFMs as highlighted in Ben Cohen's and Janick Bergeron's texts. This is analogues to SystemC's transaction level modelling concept.

I would like to know what is SystemC can provide that VHDL is lacking.

with regards,
SAHO

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I have started a listing of SystemC pro and con. Please advise.

Pro
==
1. SystemC offers constraint random stimuli generation

2. SystemC is used in evaluating system performance through system modelling

3. SystemC transaction record are easier to view in waveform (as transaction, rather than loose signals)

4. SystemC testbench runs faster than conventional HDL simulation (??)

Con
==

edge · Newbie Joined: Oct 25, 2004 Posts: 1

well, going down point by point , feature by feature seems like the wrong way to go. key points are:

1. systemc and scv 1.0 give complete C++ flexibility for modeling your environment. yes, there are specific features like stim gen and coverage, but the greater issue is being able to use real C++ and OOP for describing your environmnet (stimulus and checkers/reference model )with a real language.

2. Don't count on SystemC being much faster than VHDL, unless you are modelling at a much higher level of abstraction. That is NOT the major motivator for SysC.

3. Be prepared to pay a little $$ for a mixed lang environment (Mentor, Cadence, others? ) if you want to get real work done quickly.

4. Is your Device under test complex to benefit from the high level of abstraction of SysC and C++ ? If not, you may want to stick with your vhdl.

5. I do not believe VHDL is great for testbenches, unlike some. It does have re-entrant tasks , which is a great help over old verilog.

alexg · Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa