Virtual CPU Co Verification tool

Anoop · Senior Joined: Sep 29, 2004 Posts: 10

Can i have more inputs about Virtual CPU from Summit Design.

jra · Junior Joined: Aug 27, 2004 Posts: 5

Anoop,

Virtual-CPU has been around as a Cisco internal tool since the mid 1990's
and as a commercial tool since 1997.
I was one of the 2 developers that turned it into a commercial product for Simulation Technologies. The other was Dave Von Bank, now of Posedge Software (www.posedgesoft.com)

The key concept of V-CPU and the reason Cisco wanted to continue it's use instead of adopting a commercial product like Seamless was a feature called implicit access. With V-CPU you run the software as a native compiled C program and link a library to your program that allows bus transactions to be sent to a logic simulator containing the BFM for the processor or I/O bus. Implicit access provides a way to automatically trap your memory accesses from your C code without calling a special function. You can just write
unsigned long *ptr = 0xffff0000;
unsigned long data = 0xabcd1234;
*ptr = data; /* Write address 0xffff0000 directly */

instead of putting in special functions to call the BFM.

There is a lot more info about V-CPU and how it works in my book:

http://coverification.home.comcast.net

You can probably use the search function on Amazon to look for implicit access in the book, but it's easier to just buy the book.

Let me know if you have any other questions on V-CPU and how it works.

Jason

Anoop · Senior Joined: Sep 29, 2004 Posts: 10

Thankyou Jason for your inputs, could you please brief me a bit about ISS and ISR in VCPU.

jra · Junior Joined: Aug 27, 2004 Posts: 5

Anoop,

The ISS is a model of a microprocessor. It models in internal workings of the processor, thinks like instruction set, registers, pipeline, cache, etc.

V-CPU can use an ISS coupled with a Verilog/VHDL bus functional model of the pins of the CPU to do co-verification. The ISS runs software that is cross-compiled for the target processor, ARM, MIPS, PowerPC, etc.

ISS models vary greatly in quality, performance, and detail. The user normally uses whatever software debugger the ISS can support to control the software execution. The major difference between host-code mode (native compile of sw) and ISS is the ability to run the target instruction set (assembly code) on the ISS.

By ISR I'm guessing you mean interrupt service routine. On an ISS interrupts are modeled just as they would occur in the silicon. Interrupt pins will trigger the software to jump to an interrupt vector. In the host-code mode of V-CPU the user can register a C function to be called as an interrupt handler.

Let me know your target processor and ISS and I can probably give you some more info about what you can expect.

Jason