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unmesh
Senior
Joined: Jun 21, 2004
Posts: 11
Location: Bangalore
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 Posted: Fri Jul 30, 2004 1:26 am Post subject: connecting VERA class variables to HDL ports |
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greetings all,
am still in the process of learning vera so apologies if this query seems a little stupid. i have created a class which has a variable named RST. i also have a rtl, from which i have generated a .if.vrh file which has a port named RESET. in the class, RST is pulled high @(posedge CLOCK). i want to connect this variable RST to the RTL port RESET. the objective behind this is to include all standard stimuli in the class itself. the end user just has to create an object of the class and plug it into his design.
so how do i connect this variable to the port in my vera code file (.vr).
thanks and best regards
Unmesh |
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Logger
Senior
Joined: Jun 15, 2004
Posts: 340
Location: MN
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| Posted: Fri Jul 30, 2004 12:47 pm Post subject: Virtual Ports |
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Hi Unmesh,
What you want to do is utilize virtual ports. They provide a level of abstraction to the physical interface that allows you to do what you want.
Take this example:
| Code: | interface my_ifc {
input clk CLOCK;
output rst PHOLD #1;
input data_in PSAMPLE #-1;
output data_out PSAMPLE #1;
}
port my_port {
rst;
in;
out;
}
bind my_port dut_port {
rst my_ifc.rst;
in my_ifc.data_in;
out my_ifc.data_out;
}
class xactor {
// my_port abstracts physical link to interface out of the class
my_port p;
task new(my_port p) {
this.p = p;
}
task reset() {
// Notice no @(posedge clk) references. Utilize the implicit
// synchronization provided by the interface.
p.rst = 1'b1;
@1 p.rst = 1'b0;
}
// more class tasks
}
program test {
xactor my_xactor = new(dut_port); // pass the dut_port binding
// into the class
my_xactor.reset();
// do something
}
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unmesh
Senior
Joined: Jun 21, 2004
Posts: 11
Location: Bangalore
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| Posted: Thu Aug 05, 2004 11:05 pm Post subject: Re: Virtual Ports |
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Hi Logger
the solution is perfect. tried it and it works like a charm.
thanks and best regards
Unmesh |
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