| Login | | Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. | |
| Who's Online | There are currently, 55 guest(s) and 0 member(s) that are online.
You are Anonymous user. You can register for free by clicking here | |
 | |
|
Verification Guild: Forums |
|
| View previous topic :: View next topic |
| Author |
Message |
vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1237
Location: Los Angeles, CA
|
 Posted: Tue May 11, 2004 10:28 pm Post subject: Modeling Master/Slave latches |
 |
|
Note from the moderator: This topic was split from this topic
| Quote: | | Code: |
always @(negedge clk) begin
reg1_r <= reg1_in;
end
assign reg1_s = reg1_r;
|
This models a master/slave register. Both the master and the slave change on the same edge, but it still works in simulation the same way a real master/slave register would. ie. you can assign the reg1_s signal to another negedge clk register w/o it being a race condition. We do this to maximize simulator performance which is critical for our verification.
|
I am missing something! You mean you have code like this for simulation performance?
| Code: |
always @(negedge clk) begin
reg1_r <= reg1_in;
reg2_r <= reg1_s; // to optimiize performance?
// instead of
reg2_r <= reg1_r; // which seems more efficient
end
assign reg1_s = reg1_r; // this is another simulator evaluation
// how could that be more efficient?
// Add the fact that a wire is a resolved signal, and that may add more
// processing in simulation.
|
That's another issue. More on design than verification. I am just curious.
I must be missing a concept here???
| Quote: | The bottom line is that I still don't think we have a solution to constraining how the inputs start up for FV with the verilog coding style we use.
My example property attempting to not allow b or c to go to 1 until a went to 1 did not work. I can't explain why. I think I'm stuck for now.
|
Time to call the vendor's support! Since we got involved in this, we would like to find out your solution.
Ben
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
|
| Back to top |
|
 |
romi
Senior
Joined: Feb 28, 2004
Posts: 88
Location: Minnesota
|
| Posted: Wed May 12, 2004 5:24 am Post subject: |
|
|
| Code: | always @(negedge clk) begin
reg1_r <= reg1_in;
reg2_r <= reg1_s; // to optimiize performance?
// instead of
reg2_r <= reg1_r; // which seems more efficient
end
assign reg1_s = reg1_r; // this is another simulator evaluation
// how could that be more efficient?
// Add the fact that a wire is a resolved signal, and that may add more
// processing in simulation.
|
Your example is a race condition. You'll get unknown results. You do not know if reg2_r will get the updated value of reg1_r or the old value of reg1_r. You must add in the delta delay of assigning reg1_r to reg1_s.
However, that is not what I meant when saying it is more efficient. I meant having the master and slave clock on the same edge is more efficient than modeling it how a real master/slave latch works.
| Code: | always @(negedge clk) begin
reg1_r <= reg1_in;
end
always @(posedge clk) begin
reg1_s <= reg1_r;
end
|
In this example the simulator is solving on both the negedge and the posedge. So, when there are hundreds of thousands of latches in the design clocking on both edges, I think there ends up being more solves. So, modelling it the other way is faster. I think it may also make the compiled design smaller. And it's less typing!
Remember what my clock looks like... {clk[*3];~clk}. The slave latch is clocking 1/4 cycle after the master in real life. However, we simulate with them clocking on the same edge. The delta time delay to assign the reg1_s signal represents the 1/4 cycle delay from the real world model.
Back to the original subject. I'll let this forum know what I hear from a couple different vendors on how to solve my problem. |
|
| Back to top |
|
|
vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1237
Location: Los Angeles, CA
|
| Posted: Wed May 12, 2004 9:06 am Post subject: |
|
|
| Quote: | | Code: | always @(negedge clk) begin
reg1_r <= reg1_in;
reg2_r <= reg1_s; // to optimiize performance?
// instead of
reg2_r <= reg1_r; // which seems more efficient
end
assign reg1_s = reg1_r; // this is another simulator evaluation
...
Your example is a race condition. You'll get unknown results. You do not know if reg2_r will get the updated value of reg1_r or the old value of reg1_r. You must add in the delta delay of assigning reg1_r to reg1_s.
|
|
... Are we talking Verilog? The "<=" is a nonblocking assignment, and there is NO RACE condition. "reg2_r <= reg1_r;" WILL GET the OLD value of reg1_r.
With reg2_r <= reg1_s; will also get the OLD value of reg1_r.
But why are you involved in master/slave at the RTL design level.
Are there "funny" things in your RTL that messes up formal verification?
Maybe the issue is not formal verification but your RTL!
If there were race conditions in the nonblocking assignments, the Verilog would really be in trouble! Check your Verilog book!
Ben
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
|
| Back to top |
|
|
romi
Senior
Joined: Feb 28, 2004
Posts: 88
Location: Minnesota
|
| Posted: Wed May 12, 2004 9:37 am Post subject: |
|
|
You are right. Sorry. It ends up being a timing problem (0 phase decision, our latch is open for a 1/4 cycle) in our design not a verilog race problem. The = sign causes the race condition. Bad memory. We use the "extra" "assign reg1_s = reg1_r;" assignment to tell a downstream tool to instantiate a M/S latch. Then, in our RTL we can use the reg1_r signal if we want to use the master and the reg1_s signal if we want to use the slave. Even though they simulate the same.
I don't know what you mean by funny code. Our code looks just like my example. Is that funny? The only "funny" thing is that we don't have a reset so the FV tools need to provide us a way to specify an initial state for our regs. |
|
| Back to top |
|
|
|
|
You can post new topics in this forum
You can reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
|
| |
|
|
Forum FAQ
Search
Usergroups
Profile
Digest
Log in
