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Janick
Site Admin
Joined: Nov 29, 2003
Posts: 1382
Location: Ottawa, ON Canada
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 Posted: Fri May 14, 2004 11:16 am Post subject: |
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| vhdlcohen wrote: | | The event stuff is WAY TOO MUCH CODE!. |
As a big supporter of VHDL, I didn't expect you to complain about code volume 
| vhdlcohen wrote: | | Besides, VHDL does not support the Verilog event |
The events do not refer to Verilog events but to PSL temporal sub-expressions... as I said, I'm not familiar with PSL syntax. |
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vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1238
Location: Los Angeles, CA
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| Posted: Fri May 14, 2004 4:39 pm Post subject: |
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| Code: | event request = bus_req == 1'b1;
event grant = ack == 1'b1;
event canceled = cancel == 1'b1;
event reset = reset_n == 1'b0;
always (request |-> {[*0:5]; grant } abort (canceled || reset)); |
| Quote: | | The events do not refer to Verilog events but to PSL temporal sub-expressions... as I said, I'm not familiar with PSL syntax. |
Come to think of it, the "event" is not part of PSL, but belongs to the "Modeling layer". Per LRM, the modeling layer provides a means to model behavior of design inputs (for tools such as formal verification
tools in which the behavior is not otherwise specified), and to declare and give behavior to auxiliary signals and
variables. ... The Verilog flavor of the modeling layer consists of the synthesizable subset of Verilog, defined by IEEE standard
1364.1-2002, Standard for Verilog Register Transfer Level Synthesis.
HOWEVER, PSL exect Boolean expression and named events will NOT work. Thus, the assertion that uses those event will not work!
BTW, that also applies to SVA -- no named events in expression of properties. You might be able to use events in the "disable iff" statement .. not sure, perhaps someone knows.
Thus, need to use either using the implicit values of objects (i.e., {a; !b} or the explicit values (i.e., {a==1'b1; b==1'b0} .
While I am on the BTW subject, the SystemVerilog LRM uses in the examples the implicit values, as in "a ##1 b ##1 c // first sequence seq1"
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
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