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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 57 guest(s) and 1 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  UVM register models generation          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message tsengr Senior Joined: Aug 11, 2006 Posts: 53 Posted: Thu Apr 05, 2012 6:12 pm    Post subject: UVM register models generation Hi, Is there a decent, free, and reliable tool that would read a text format register file and generate the UVM register models? Thanks, Richard Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Thu Apr 05, 2012 11:47 pm    Post subject: Re: UVM register models generation tsengr wrote: Hi, Is there a decent, free, and reliable tool that would read a text format register file and generate the UVM register models? Thanks, Richard Check out http://www.agnisys.com/products/66-idsfree - right from DOC file you can do this. HTH Ajeetha, CVC www.cvcblr.com/blog _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top ericswa Junior Joined: Feb 29, 2012 Posts: 5 Posted: Thu Apr 12, 2012 10:21 am    Post subject: Another option is to use an open-source tool (spec2reg) from Paradigm Works. You save an MSWord .doc as .xml, and the tool parses/extracts registers to generate VMM RALF file. Spec2reg is perl code, and wasn't too hard to change the code in order to add features to our RALF file; any other output file can also be generated (C, UVM RALF, verilog). BTW, the output files are created/formatted in the template files (*.tt). http://www.paradigm-works.com/products/index.shtml - EDS Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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