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kfathy2002
Newbie
Joined: Mar 26, 2012
Posts: 3
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 Posted: Wed Apr 11, 2012 12:53 pm Post subject: Controlling random variables from test case |
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Hi All,
How can i control a random variable in the configuration class to have a default value and to be another value only when needed,
as an example:
in a verification environment, i want to add a new configuration variable, this variable needed to carry Zero at any test case, while at a certain test case, it should carry ONE. |
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Ajeetha
Senior
Joined: Mar 29, 2004
Posts: 424
Location: Bengaluru, India
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| Posted: Sat Apr 14, 2012 9:24 am Post subject: Re: Controlling random variables from test case |
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| kfathy2002 wrote: | Hi All,
How can i control a random variable in the configuration class to have a default value and to be another value only when needed,
as an example:
in a verification environment, i want to add a new configuration variable, this variable needed to carry Zero at any test case, while at a certain test case, it should carry ONE. |
Classical case for UVM/VMM factory.
| Code: |
class cfg_c extends uvm_object;
`uvm_object_utils(cfg_c)
rand bit [3:0] bit_0;
constraint cst_default { this.bit_0 == 3'b000;}
endclass : cfg_c
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In a specific testcase:
| Code: |
class my_cfg_c extends cfg_c;
`uvm_object_utils (my_cfg_c)
constraint cst_default { this.bit_0 == 3'b001;}
endclass : my_cfg_c
class my_test extends my_proj_base_test;
task build_phase (uvm_phase phase);
my_cfg_c = new; // use factory/create if you like
factory.set_override_by_type (.orig_type(cfg_c::get_type),
.override_type(my_cfg_c::get_type));
endtask : build_phase
endclass : my_test
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Does that help you?
Ajeetha, CVC
www.cvcblr.com/blog
_________________
Ajeetha Kumari,
CVC Pvt Ltd. http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar |
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kfathy2002
Newbie
Joined: Mar 26, 2012
Posts: 3
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| Posted: Sun Apr 15, 2012 8:06 am Post subject: Thanks |
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yes it's very helpful,
Thanks Ajeetha. |
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