SystemVerilog Assertion - is it allowed to use real values

Andi

Hi folks,

if I read the SV LRM, my understanding is that it is not allowed to use any veriables of type 'real' inside a concurrent assertion.
Do you agree to this?
Do you know why this is forbidden?

All the best
Andreas

Swapnajit · Senior Joined: Sep 21, 2004 Posts: 16

From IEEE Std. 1800-2009

dave_59 · Posted: Wed Feb 01, 2012 11:23 pm **Post subject:**

Andreas,

The original writers of the SystemVerilog LRM were thinking about the synthesis that happens when implementing concurrent assertions. It turns out that Boolean expressions don't need to be synthesized. Only the resulting temporal expressions that are turned into state machines need to be synthesized.

In the upcoming SV 1800-2012 LRM, they have relaxed these restrictions so that you can use most data types within an expression as the overall expression can be cast to an integral type.

Some simulators, like Questa, already support this.

Dave Rich
Mentor Graphics

Andi · Posted: Mon Feb 13, 2012 3:03 am **Post subject:**

Hi Dave,

many thanks for your explanation.
However, I just have had a look at the latest draft D3, Nov 5th 2011, for the upcoming version. In section 16.6.1 I can still find the following:

dave_59 · Posted: Mon Feb 13, 2012 3:10 am **Post subject:**

It's in Draft 4, which is the latest. D5, the ballot draft, is about to be released.

See http://www.eda.org/svdb/view.php?id=2328 for the change.

Dave Rich
Mentor Graphics