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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 35 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Condition Based covergroup implementation          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message SKS Junior Joined: Dec 15, 2011 Posts: 5 Posted: Thu Feb 09, 2012 8:04 am    Post subject: Condition Based covergroup implementation Hi , We can have condition based coverpoint implementaion for coverage in system verilog. Can we have condition based covergroup implementaion ???? If yes, then How ???? Regards, Saurabh Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Sat Feb 11, 2012 3:56 am    Post subject: Re: Condition Based covergroup implementation SKS wrote: Hi , We can have condition based coverpoint implementaion for coverage in system verilog. Can we have condition based covergroup implementaion ???? If yes, then How ???? Regards, Saurabh Maybe you can sample it based on the condition? Use explicit sampling via sample() method. Ajeetha, CVC www.cvcblr.com/blog _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top SKS Junior Joined: Dec 15, 2011 Posts: 5 Posted: Sat Feb 11, 2012 4:58 am    Post subject: Re: Condition Based covergroup implementation Hi, Even if i do not sample it, it would be present in coverage report and that will lead to have less overall coverage. I want to completely exclude a particular covergroup based on some condition. ????? Regards, SKS Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Sat Feb 11, 2012 10:26 am    Post subject: Re: Condition Based covergroup implementation SKS wrote: Hi, Even if i do not sample it, it would be present in coverage report and that will lead to have less overall coverage. I want to completely exclude a particular covergroup based on some condition. ????? Regards, SKS Is that condition compile/elab time or run time variable? If compile time - you can use `ifdef, if elab time you can use generate. If run time - you can use "coverage exclusion" flow as some form of post-processing (check your tool doc). HTH Ajeetha, CVC www.cvcblr.com/blog _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top dave_59 Senior Joined: Jun 22, 2004 Posts: 974 Location: Fremont, CA Posted: Sat Feb 11, 2012 2:49 pm    Post subject: You can always set the weight the covergroup to 0, that has the effect of removing it from the overall coverage calculation. When is this condition known? And is the result of the condition available when constructing the covergroup. Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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