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edalearner
Senior
Joined: Apr 02, 2007
Posts: 75
Location: Shanghai, China
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 Posted: Fri Dec 09, 2011 3:58 am Post subject: hierarchical expression in clocking block |
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Hi forum,
Just wondering why I can't write
| Code: |
interface foobar_if ( input clk, inout foobar );
clocking cb @ ( posedge clk );
input foobar_n = ~ foobar;
endclocking
endinterface
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The P1800 section 14.5 says that
| Quote: |
In a clocking block, any expression assigned to a signal in its declaration shall be an expression that would
be legal in a port connection to a port of appropriate direction. Any expression assigned to a signal in a
clocking input or inout declaration shall be an expression that would be legal for connection to a module’s
input port. Any expression assigned to a signal in a clocking output or inout declaration shall be an
expression that would be legal for connection to a module’s output port.
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Thanks,
Robert |
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dave_59
Senior
Joined: Jun 22, 2004
Posts: 974
Location: Fremont, CA
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| Posted: Fri Dec 09, 2011 1:29 pm Post subject: |
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| There seems to be some conflicting statements in the LRM. The BNF allows any expression, but the text of the LRM only allows an identifier. See http://www.eda.org/sv-ec/hm/8312.html. |
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shalom
Senior
Joined: Jan 06, 2004
Posts: 110
Location: Jerusalem, Israel
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| Posted: Mon Dec 12, 2011 3:05 am Post subject: |
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The change from 'hierarchical_identifier' to 'expression' in the BNF was deliberately made, as described in Mantis 595 (http://www.eda-stds.org/mantis/view.php?id=595). It is clear that no one noticed the text referring to hierarchical_identifier, which also should have been updated.
Regards,
Shalom
_________________
Shalom Bresticker
Senior CAD Engineer, Intel
Jerusalem, Israel
http://il.linkedin.com/in/shalombresticker |
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