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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 56 guest(s) and 1 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Question: Operators in Assertions          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message spartanthewarrior Senior Joined: Aug 15, 2009 Posts: 32 Posted: Tue Apr 03, 2012 1:48 am    Post subject: Question: Operators in Assertions Hi All, Can any body which operator I should use in System Verilog assertions, Logical or Bitwise....and Why ?? Back to top sharanbr Senior Joined: Sep 27, 2004 Posts: 194 Posted: Tue Apr 03, 2012 9:02 am    Post subject: all regular operators are supported (except a few specified by the LRM) in assertions. I would assume, the usage will depend on actual application. For example (untested code ...) Code: (2_bit_vec == 2'b01) && ($past(2_bit_vec) == 2'b00) |=> (2_bit_vec & 2_bit_vec_mask) == 2'b11 Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Tue Apr 03, 2012 11:43 am    Post subject: Re: Question: Operators in Assertions spartanthewarrior wrote: Hi All, Can any body which operator I should use in System Verilog assertions, Logical or Bitwise....and Why ?? You can use both. However in many use cases it is the bit-wise that's likely to be a better fit. See some related articles at: http://www.cvcblr.com/blog/?p=377 http://www.eda.org/svdb/view.php?id=2938#c9555 HTH Ajeetha, CVC www.cvcblr.com/blog _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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