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naajila
Senior
Joined: Nov 30, 2010
Posts: 30
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 Posted: Wed Mar 09, 2011 11:27 am Post subject: Generation of clock |
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I want to create one Monitor which recieves a clock1 from RTL.
Again i have to reciev eone more signal x from RTL .When x becomes 1, "data" has to be collected at both posedge as well as negedge of clock1.
x may come at any time (either at posedge or negedge or in middle of these edges of clock1)..When it comes 1,immediately at next edge(may be posedge or negedge) i have to collect data.
So i want to generate one more clock clk2 in my monitor whcih has the time period exactly half of clock1.
My intension to generate clk2 ::: To collect the data always at posedge of clk2 so that i dont have any confusion of posedge or negedge of clk1.
Can anybody write a logic to generate this clk2 and it should be in synchronization with clk1.? |
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alexg
Senior
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Joined: Jan 07, 2004
Posts: 586
Location: Ottawa
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| Posted: Wed Mar 09, 2011 1:43 pm Post subject: |
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Not sure why you need a second clock.
This code may be sufficient for your needs:
| Code: | always @(clk1) if(x) begin
d1 <= data;
@(clk1) d2 <= data;
end |
-Alex |
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