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vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1161
Location: Los Angeles, CA
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 Posted: Wed Jun 02, 2010 11:57 am Post subject: DvCon2010 paper code update |
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I updated the checker code for my DvCon2010 on using checkers for a cache controller design. There are two models, one with the IEEE 1800-2009 checker and one using assertions within the module, without the checker (see http://systemverilog.us/DvCon2010/ ).
The error I corrected is the type of the formal argument clk. It should be event instead of logic. Per IEEE 1800-2009 | Quote: | ... each formal argument shall be assigned the sampled value of its actual argument during the Preponed region of each time step, with the following exceptions:
... Arguments that cannot be sampled, such as events, sequences, and properties, are treated similarly to such arguments for sequences and properties: they are substituted directly for the formal argument when it is used in statements or expressions within the checker. |
When typing "clk" as "logic", that argument gets sampled. This is not what is needed. Apologies for the mistake.
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 2nd Edition, 2010
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
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