Future of EDA & ASIC vs FPGAs

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.19, Item 3.0)

From: Anonymous

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

From: Tom Moxon

"Ah yes, sometimes it is difficult for one standing on a mountain top,
above the clouds, to predict the weather on the ground..."

While it is true that FPGA vendors such as Xilinx and Altera are
investing heavily in their proprietary tools for FPGA design (ISE and
Quartus II, respectively), they still have some ground to cover before
they are at the same level with most of the mainstream ASIC design
tools. XST (Xilinx Synthesis Tool) while a workable synthesis tool,
doesn't produce the quality of results found using Synplicity or
Mentor synthesis tools, for example. So I disagree with Erach Desai's
assertion that it is an "either/or" relationship between FPGA vendor
tools and mainstream ASIC design tools. Most serious design houses
purchase both, and routinely use both. Many designers prototype their
ASIC designs using an FPGA first, to work out design and interface
issues before committing the heavy investment required for an ASIC
version of the design.

The real culprit in the decline of ASIC design starts, and thus EDA
tools sales, is the ballooning price of semi custom and full custom
mask sets and prototype NRE's - as the industry moves from 130nm, to
110nm, and down to 90nm design geometry's.

In the good old 800nm days, if you could scrape together $100K or so,
you could easily pay for an ASIC design and get into small scale
production. Now the cost of entry is easily $1 Million and can often
exceed $10 Million when you include EDA tools, engineers, and a few
prototype runs.

When you compare this with a paltry $5,000 or so to get an FPGA
vendors toolset and development board, it is easy to see why the low
and medium volume customers are using CPLD's and FPGA's whenever they
can, and reserving the ASIC design starts for really high volume
parts, and those with technical requirements that absolutely demand an
ASIC design.

Adding another wrinkle to Mr. Desai's prediction is the resurgence of
"Structured ASIC" design flows (old-timers would call them Gate-Arrays
...) where only top level metalization masks are required, and so the
NRE's drop back to a more palatable range again. Several vendors are
now releasing these product families to try and win back volume
production from the FPGA vendors.

Finally, there is also a growing need for better capacity,
integration, and Signal Integrity "awareness" in EDA tools as we move
down to 90nm; and frankly, many of the older EDA tools have just "run
out of stream" at 90nm. This is why we see companies like Magma and
Monterey gaining market share (and mind share) with ASIC
designers. These are not just "cobbled together point tools", but a
real set of common engines running on a integrated database to
simultaneously solve signal integrity, physical design rules, and
timing issues. The EDA industry is now evolving to the next generation
- and that is never easy process, and usually results in a drop in
sales until the winners and losers are sorted out..

- Tom Moxon
Moxon Design

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

From: Dave Chapman