Verification Guild
A Community of Verification Professionals

 Create an AccountHome | Calendar | Downloads | FAQ | Links | Site Admin | Your Account  

Login
Nickname

Password

Security Code: Security Code
Type Security Code
BACKWARD

Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name.

Modules
· Home
· Downloads
· FAQ
· Feedback
· Recommend Us
· Web Links
· Your Account

Advertising

Who's Online
There are currently, 48 guest(s) and 0 member(s) that are online.

You are Anonymous user. You can register for free by clicking here

  
Verification Guild: Forums

 Forum FAQForum FAQ   SearchSearch   UsergroupsUsergroups   ProfileProfile  ProfileDigest    Log inLog in 

Reference vs behavioral model

 
This forum is locked: you cannot post, reply to, or edit topics.   This topic is locked: you cannot edit posts or make replies.    Verification Guild Forum Index -> Simulation
View previous topic :: View next topic  
Author Message
Newsletter
Original Contribution


Joined: Dec 08, 2003
Posts: 1107

PostPosted: Mon Dec 01, 2003 12:00 am    Post subject: Reference vs behavioral model Reply with quote

(Originally from Issue 4.18, Item 7.0)

From: Anonymous

Are reference model and behavioural model synonyms?

Can I always use a behavioural model as a reference model? Or is
there some requirements how a reference model should be designed when
I want to use it as a golden model, to compare results between the
golden model and RTL code.
Back to top
View user's profile
Newsletter
Original Contribution


Joined: Dec 08, 2003
Posts: 1107

PostPosted: Wed Dec 17, 2003 5:40 pm    Post subject: Reference vs behavioral model Reply with quote

(Originally from Issue 4.19, Item 1.0)

From: Scott Meeth

Answer to first question: no. Here's what my experience has left me believing:

Similarities:

Each is a simulation-only creature, and we are only interested in the behaviour at the interface of the model.

Differences:

A behavioural model normally interacts with something in such a manner as to affect the operation of the DUT (Design under test). It is meant to abstract out some details which are not interesting to simulation (e.g. manufacturing details of the DUT, or the implementation of some device which interacts with the DUT). It might model something in the DUT (e.g. an SRAM), in which case it will interact with other blocks of the DUT. Or it might model a device external to the DUT (e.g. an IO device or a processor), in which case it will interact with the DUT itself, perhaps fulfilling its requests. This latter type of behavioural model is often used to provide stimulus to a DUT in simulation.

A reference model normally models the expected behaviour of the DUT at the interface, in a sense abstracting out all of the implementation details of the DUT and just exhibiting its behaviour. Given a stimulus, it is run in parallel with the DUT (independent of it), and the output of the reference model is compared with that of the DUT.

So I guess the main difference is that behavioural models tend to *affect* the operation of the DUT (model some part of the DUT, or some device that interacts with the DUT), whereas reference models tend to produce *independently* the expected behaviour of the DUT.

Answer to second question: I think it would be dangerous to do this. An example of this situation would be a processor project which developed a behavioural model of an IO device for their verification environment, and then the IO device project wants to use the behavioural model as a reference model.

The behavioural model was designed for the purpose of providing stimulus to, and reacting to stimulus from, the processor. It may (and often will) exhibit behaviour outside of the spec of the IO device, for any number of reasons (they may just want to verify more aggressively, they may have multiple customers). Furthermore, a behavioural model is normally an interactive creature, whereas a reference model is self-contained This difference in mindset can propagate, to have unexpected consequences.

In any case, the behavioural model was designed for a specific purpose (verification of the processor), and that purpose is orthogonal to the purpose for which the IO team would want to use it (behaviour reference for IO device). Using something for a purpose other than that for which it is designed is always a risky endeavour.
Back to top
View user's profile
Newsletter
Original Contribution


Joined: Dec 08, 2003
Posts: 1107

PostPosted: Mon Jan 05, 2004 10:35 pm    Post subject: Reply with quote

From: Kamal Hashmi


The first thing here is a confusion about terminology. The term
'Reference Model' defines what it's used for, whereas 'Behavioural
Model' defines how it's been implemented. There is a tendency
nowadays to use 'Behavioural' to mean a model somewhere above RTL and
below Untimed Functional. (I am partly to blame as I didn't fight
strongly enough when the VSIA SLD Model Taxonomy was being rewritten
from the RASSP Taxonomy). Anyway, this is not a small space ... so I
encourage people to use less vague terms.

A 'Reference Model' can be used as a 'Golden Model' if you've
validated and verified it to whatever your Quality requirement for
Goldness is
level.

'Reference Models' usually have some constraints on the region of the
design space in which they act as reference models, for example if
you're doing multi-level design (I mean levels of abstraction not
hierarchy) then each higher-level model would act as a functional
reference model for the equivalent lower-level model. The TestBenches
for the higher level model should at least be able to be used with the
lower level model. Ideally, you should be able to verify that the
design space of the lower level model was a subset of the higher level
model.

- Kamal Hashmi, Director Technology
SpiraTech Ltd
Back to top
View user's profile
Newsletter
Original Contribution


Joined: Dec 08, 2003
Posts: 1107

PostPosted: Mon Jan 05, 2004 10:37 pm    Post subject: Reply with quote

From: Michael Meredith

I would define a behavioral model of a module to be a module that
abstracts out the implementation details while maintaining the
accuracy of the interface.

Such a model might be built to experiment with various algorithms or
with various interface schemes. Such a model might be built to permit
high performance simulation of the enclosing system. Such a model
might be built for implementation using behavioral synthesis. Each of
these uses will require different levels of completeness and
correctness of the behavior.

I interpret the intent of the original question to be "If I build a
behavioral model of a particular module for any of these purposes, can
I use it as a reference for verification of an eventual RTL
implementation of the same module?".

I think that depends on how accurately you modeled the behavior. In
order to use a behavioral model as a reference model, you must be
confident that the behavioral model exhibits the desired behavior
under all circumstances.

In some cases, as Scott Meeth points out, you may have built the model
for a purpose that only requires a subset of the functionality. This
model may not be appropriate for use as a reference model.

One design flow includes construction of a complete system at the
behavioral level by building a behavioral model of each module. In
order use this to validate system behavior, each module must
accurately implement all required behaviour.

In this flow, each of these models is appropriate to be used as a
reference model for a unit test of an RTL implementation of the same
module. The behavioral model of the rest of the system can be used to
provide stimulus.

<Plug for my company's technology>
This kind of verification approach works well in an environment where
some of the modules are appropriate to be implemented using
behavioral synthesis. In this case, the original behavioral
description can used as the basis for the behavioral implementation
model, avoiding redundant design effort.
</Plug>
Back to top
View user's profile
Display posts from previous:   
This forum is locked: you cannot post, reply to, or edit topics.   This topic is locked: you cannot edit posts or make replies.    Verification Guild Forum Index -> Simulation All times are GMT - 5 Hours
Page 1 of 1

 
Jump to:  
You can post new topics in this forum
You can reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
Verification Guild © 2006 Janick Bergeron
Web site engine's code is Copyright © 2003 by PHP-Nuke. All Rights Reserved. PHP-Nuke is Free Software released under the GNU/GPL license.
Page Generation: 1.303 Seconds