How to avoid duplicate modules in Verilog

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.18, Item 10.0)

From: Anonymous

I have a specific problem

Normally in a test set-up, a RTL and test model will be present. In
my particular case (exception), I have two instances of the RTL model.

My test set-up is fine when running test cases etc etc. But when I do
gate simulations, since I have two instances of RTL, two modules with
same name are seen by the compilier. I want to avoid it.

One simple way to avoid it is by changing the name of the files. Is
there any other method that can be used with out changing the
names?

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.19, Item 9.0)

From: Laurent Claudel

Which Verilog simulator are you using ?

Most compiler provide a way to have different views of a same module and while elaborating your design, you can choose which view you're using. Thus you can compile one instance in a view called rtl and the other one in a view called gate and you will have my_design:rtl and my_design:gate. And when you elaborate your design with your bench, you choose in your setup file which view should be used with the bindings. It is pretty much straight forward with NCsim.

This method as been actually normalized with the configuation feature of Verilog2001 (but your compiler may not support it yet) where each module has a symbolic notation lib.cell:config