Looking for practical "Design for Verification" articles

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.16, Item 6.0)

From: Ahuja Vikas

I have gone through the first edition of "Writing Testbenches,
functional verification of HDL models". In the book, I read about the
interesting topic of Design for Verification. I have tried to search
various sites including IEEE for finding more about this topic and
possible practical implementations for integrating this in the
functional verification flow. Some of the articles talked about how to
save some simulation cycles by adding controllability on hard to
control conditions.variables in HDLs. Some of Synopsys articles
talked about use of assertions a s a part of DFV methodology. I agree
that assertions are being used widely in the industry.

Can you point me to some indepth articles on "design for
verification", which also address practicability aspect of the
solutions?

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.17, Item 3.0)

From: Steven Jorgensen

Have you read "Principles of Verifiable Design" by Bening and Foster
Published by Kluwer?

- Steven Jorgensen, Hardware Design Engineer, HP

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.17, Item 3.1)

From: Donna Mitchell

"Coding Techniques for Bus Functional Models in Verilog, VHDL, and
C++" at http://www.syncad.com/paper_coding_techniques_icu_sep_2003.htm
discusses techniques for creating hierarchical test benches that
support re-use at different stages during the design of large-scale
systems. A generic test bench architecture is described that can be
implemented using either Verilog, VHDL, or C++, with notes on
techniques required by the quirks of each language.

Some of the techniques that are covered include race avoidance,
handling of multiple clock domains, lookup techniques for emulating
hierarchical references to BFMs in VHDL, emulation of "class-like"
data structures in Verilog and VHDL, and the use of a golden reference
model to verify functionality while testing a system against
constrained-random data.

- Donna Mitchell, SynaptiCAD