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svBitVecVal as reference in SV LRM 1800-2009

 
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shwink
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Joined: Dec 23, 2011
Posts: 1

PostPosted: Fri Dec 23, 2011 1:48 am    Post subject: svBitVecVal as reference in SV LRM 1800-2009 Reply with quote

Hello All,

Going through the SV LRM 1800-2009, under the section H.7.4 Basic types,

The description was as below.

The input mode arguments of type byte unsigned and shortint unsigned are not equivalent to
bit[7:0] or bit[15:0], respectively, because the former are passed as C types unsigned char and
unsigned short and the latter are both passed by reference as svBitVecVal types. A similar lack of
equivalence applies to passing such parameters by reference for output and inout modes, e.g.,
byte unsigned is passed as C type unsigned char* while bit[7:0] is passed by reference as svBitVecVal.

my doubt here is the last statement [e.g.] "byte unsigned is passed as C type unsigned char* while bit[7:0] is passed by reference as svBitVecVal"
Is it not svBitVecVal* for bit[7:0] ?? Question

Any help in understanding this is appreciated Smile

Thanks
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Ajeetha
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Joined: Mar 29, 2004
Posts: 424
Location: Bengaluru, India

PostPosted: Sun Dec 25, 2011 10:32 am    Post subject: Re: svBitVecVal as reference in SV LRM 1800-2009 Reply with quote

Hi,

shwink wrote:
Hello All,

Going through the SV LRM 1800-2009, under the section H.7.4 Basic types,
[SNIP]

my doubt here is the last statement [e.g.] "byte unsigned is passed as C type unsigned char* while bit[7:0] is passed by reference as svBitVecVal"
Is it not svBitVecVal* for bit[7:0] ?? Question

Any help in understanding this is appreciated Smile

Thanks


Sounds to me like a typo error in LRM text, as in another section 8.8 it says:

SV LRM wrote:

inout and output arguments, with the exception of open arrays, are always passed by reference. Specifically,
packed arrays are passed, accordingly, as svBitVecVal* or svLogicVecVal*


Perhaps a good Mantis to file and get this fixed in next revision.

Ajeetha, CVC
www.cvcblr.com/blog
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Ajeetha Kumari,
CVC Pvt Ltd. http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
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dave_59
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Joined: Jun 22, 2004
Posts: 974
Location: Fremont, CA

PostPosted: Sun Dec 25, 2011 11:10 pm    Post subject: Reply with quote

Already fixed in P1800-2012. See http://www.eda.org/svdb/view.php?id=3599
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