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c++ class and SV

 
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Shail
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Joined: Mar 18, 2005
Posts: 44

PostPosted: Fri Dec 07, 2007 7:24 pm    Post subject: c++ class and SV Reply with quote

Hi,

Is there anyway, I can pass a C++ class back and forth between c++ and SV, may be via DPI ?

I am looking for an example of this.
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Logger
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Joined: Jun 15, 2004
Posts: 348
Location: MN

PostPosted: Fri Dec 07, 2007 10:55 pm    Post subject: Reply with quote

Not directly. The DPI is function based, and it doesn't map C++ class members to any form that can be directly access as a class member in SV.

You can pass the object pointer to SV, hold it there, and pass it back to C++. Which by itself sometimes has a purpose. But if your intent is to access the same class as if it is an object that is accessible from both languages, you'll have to build an interface. Which you could do using DPI.
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Shail
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Joined: Mar 18, 2005
Posts: 44

PostPosted: Sat Dec 08, 2007 1:48 pm    Post subject: Reply with quote

Thanks. I am ok passing objects pointers around and there is no need to have C++ and SV work on the same pointer.

I am looking for an example.

My env would be a mix of SV,C++ and Verilog with SV used in part of verif environment that deals with classes and at the same time, use it as driver to the RTL .

Thanks !!!
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dave_59
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Joined: Jun 22, 2004
Posts: 981
Location: Fremont, CA

PostPosted: Sat Dec 08, 2007 6:57 pm    Post subject: Reply with quote

You should get your hands on this paper from DVCon'07

5.1 Inter-Language Function Calls between SystemC and SystemVerilog Rich Edelman, Mark Glasser, Arnab Saha, Hui Yin - Mentor Graphics Corp.

Dave
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Shail
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Joined: Mar 18, 2005
Posts: 44

PostPosted: Tue Dec 11, 2007 3:50 pm    Post subject: Reply with quote

Thanks Dave.

I will look at that paper.
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Simon
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Joined: Jun 04, 2004
Posts: 64
Location: Ottawa

PostPosted: Wed Dec 12, 2007 3:18 pm    Post subject: Reply with quote

Hi Shail,

You need to write C wrapper for each of the methods of the C++ object you are trying to access. Here is a really simple example :

C ++

Code:


class foo
{
   foo() {
      // ...
   }
   virtual ~foo() {
      // ...
    }

}



C Wrappers

Code:


// Constructor wrapper
//
#ifdef __cplusplus
extern "C" void* foo_new()
#else
  void* foo_new()
#endif
{
  return new foo();
}

// Destructor wrapper
//
#ifdef __cplusplus
extern "C" void foo_free(void* inst)
#else
     void* foo_free(void* inst)
#endif
{
  foo *foo_inst = (foo *) inst;
  delete foo;
}


SV code

Code:


import "DPI-C" function chandle foo_new();
import "DPI-C" function void foo_free(input chandle inst);

program automatic prog();

   chandle foo_handle;

initial begin
    // Allocate an free a foo object
    foo_handle = foo_new();
    foo_free(foo_handle);
end

endprogram



Don't know if this help, I haven't looked at the paper Dave mentionned, maybe it has better details.

Simon
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Shail
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Joined: Mar 18, 2005
Posts: 44

PostPosted: Thu Dec 13, 2007 11:11 pm    Post subject: Reply with quote

Thanks.

This does help ..but now I am starting to have second thoughts about using sv.

I have a legacy c++ code and I have to do this for all that , it is a no no.

I hoped, DPI would work with C++ directly and could pass struct or class between c++ class and SV class.
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dave_59
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Joined: Jun 22, 2004
Posts: 981
Location: Fremont, CA

PostPosted: Thu Dec 13, 2007 11:24 pm    Post subject: Reply with quote

It doesn't have to be that hard. It the same as communicating a C struct between C and C++. You can pass structs by value or by reference through the DPI as long as the struct contains data type that are compatible with each other.

Dave
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heritageorchard
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Joined: Feb 22, 2005
Posts: 123
Location: Boston, Ma

PostPosted: Fri Dec 14, 2007 9:43 am    Post subject: C++ versus SystemVerilog Reply with quote

Hi Shail,

So what are you motivations for moving to SV? That may help focus a discussion.
_________________
Mike Mintz
www.trusster.com

"Teal and Truss" A multi-vendor, multi-language, open source verification framework
co-author "Hardware Verification with C++", and "Hardware Verification with SystemVerilog"
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Shail
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Joined: Mar 18, 2005
Posts: 44

PostPosted: Fri Dec 14, 2007 1:13 pm    Post subject: Reply with quote

Few are:

1. One language for Design and Verifcation - so no more foreign language interface (ironiacally, I will have to deal with one in process of transition)

2. Excellent randomization capabilities.. Stable and convenient ....

3. Buit-in Assertion and Coverage facilities

4. Predefined methodologies

5. choice of timed or timeless components

I could write few more but would be too detailed then..

Following are not motivations, but a past concerns , that are now solved:
1. Tool support from all vendors
2. Many users and hence nice support from forums like current one


By the way, it could be my biased thinking of complexity in using dpi to merge c++ and sv, but I am still wonding for a working example, where a
c++ class transaction, instantiated in another c++ class, being sent to SV module and SV class.

Here is my code:
sv:
Code:
class myTrans {
  unsigned int addr;
  unsigned int data;
 
  constraint c_addr { addr inside {0:100};
}

class stimGen {
  myTrans trans;
  trans = new();
  trans.randomize();
}


module driver (interface)
  //take the transaction and drive data to duv;
endmodule;

c++ code:
Code:
class myTrans {
  u_int32 addr;
  u_int32 data;
}
class model {
   process(myTrans* trans) {
    //process Trans
  }
}

How do I pass myTrans from StimGen(SV) to model(c++) and then from c++ model, onto to driver...(sv)
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chrisspear
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Joined: Jun 15, 2004
Posts: 202
Location: Marlboro, MA

PostPosted: Fri Dec 14, 2007 4:39 pm    Post subject: Reply with quote

Here is one possible version of a solution of connecting SystemVerilog and C++ code.

The big issue is passing objects back and forth across the DPI. Since there is no way to map the layout of properties between the two languages, I just passed addr and data individually. You could also pack them up in SystemVerilog and try to match the layout in C++. That is left as an exercise for the reader!

The next issue is that the DPI can only call static methods, not dynamic ones in a class. So I created methods outside the class that also accept a handle to the model object. This way you could have multiple models instantiated.


Code:
#include <svdpi.h>
#include <veriuser.h>      // Needed for io_printf
#include "vc_hdrs.h"         // VCS specific header
typedef unsigned int u_int32;

class myTrans {
public:
  u_int32 addr;
  u_int32 data;
};


class model {
public:
  model();
  void process(u_int32* addr, u_int32* data);
};

model::model()
{
  io_printf("C++: Constructing a model\n");
}

void model::process(u_int32* addr, u_int32* data)
{
  io_printf("C++: processing %x %x\n", addr, data);
  *addr = *addr + 1;
  *data = *data + 2;
}


#ifdef __cplusplus
extern "C" {
#endif

////////////////////////////////////////////////////////////////////////
// The DPI needs a static C routine to communicate with.
// This one constructs the model object and returns a handle
void* model_new()
{
  return new model;
}

////////////////////////////////////////////////////////////////////////
// Tell the model to process a transaction
void model_process(void* inst, u_int32* addr, u_int32* data)
{
  model* m = (model *) inst;
  /* Pass the individual trans properties over.
     You could also construct a trans and pass it instead */
  m->process(addr, data);
}

#ifdef __cplusplus
}
#endif


Now in the SystemVerilog code I have a class that wraps around this static interface, hiding it from the user.

Code:
typedef bit [31:0] u_int32;

class myTrans;
   rand u_int32 addr;
   rand u_int32 data;

   constraint c_addr { addr inside {[0:100]}; }
endclass // myTrans


import "DPI-C" function chandle model_new();
import "DPI-C" function void model_process(input chandle inst, inout u_int32 addr, data);

   class Model;
      chandle inst;
     
      function new();
    this.inst = model_new();
      endfunction : new

      function void proc(myTrans trans);    // "process" is reserved keyword
    model_process(this.inst, trans.addr, trans.data);
      endfunction : proc
   endclass : Model


class stimGen;
   myTrans trans;
   Model model;

   function new();
      model = new();
   endfunction : new

   
   task run();
      trans = new();
      trans.randomize();
      $display("SV : pre_process : trans.addr=%x, trans.data=%x", trans.addr, trans.data);
      model.proc(trans);
      $display("SV : post_process: trans.addr=%x, trans.data=%x", trans.addr, trans.data);
   endtask // run

endclass // stimGen


program automatic test;

   stimGen sg;
   initial begin
      sg = new();
      sg.run();
   end

endprogram : test


This is based on a 7-bit counter example that I created for the next edition of my book, SystemVerilog for Verification, which will have a new chapter on the DPI. This should be published in the spring of 2008.
_________________
Chris Spear
Co-Author: SystemVerilog for Verification - 3rd edition!
http://chris.spear.net/systemverilog
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