SystemVerilog as a modeling language?

tessitd · Senior Joined: Sep 05, 2006 Posts: 286 Location: Colorado

To all,

Well someone asked me if I could model some DSP algorithms in SystemVerilog. I said sure we could do that - we are modeling some hardware we don't have that would have performed this function.

So I started looking the LRM and noticed that there is no real MATH library!!! Is this true that I cannot use sin(x) and such? Is my only recourse to use a DPI call to 'C' and link this in?

Thanks in advance,
TomT...

RCIngham · Posted: Tue Nov 21, 2006 4:31 am **Post subject:**

As has been pointed out in other threads, SV is a super-set/extension of "vanilla" Verilog. If sine or any other desireable function exists in Verilog, you can use it in SV.

I've modelled DSP algorithms in VHDL, by using the IEEE 'math_real' package, but that may not help you.

shalom · Posted: Wed Nov 22, 2006 10:55 am **Post subject:**

Verilog-2005 defines the following real math functions as well as the intger ceiling log base2 function $clog2(x):

Table 17-18—Verilog to C real math function cross-listing
Verilog function Equivalent C function Description
$ln(x) log(x) Natural logarithm
$log10(x) log10(x) Decimal logarithm
$exp(x) exp(x) Exponential
$sqrt(x) sqrt(x) Square root
$pow(x,y) pow(x,y) x**y
$floor(x) floor(x) Floor
$ceil(x) ceil(x) Ceiling
$sin(x) sin(x) Sine
$cos(x) cos(x) Cosine
$tan(x) tan(x) Tangent
$asin(x) asin(x) Arc-sine
$acos(x) acos(x) Arc-cosine
$atan(x) atan(x) Arc-tangent
$atan2(x,y) atan2(x,y) Arc-tangent of x/y
$hypot(x,y) hypot(x,y) sqrt(x*x+y*y)
$sinh(x) sinh(x) Hyperbolic sine
$cosh(x) cosh(x) Hyperbolic cosine
$tanh(x) tanh(x) Hyperbolic tangent
$asinh(x) asinh(x) Arc-hyperbolic sine
$acosh(x) acosh(x) Arc-hyperbolic cosine
$atanh(x) atanh(x) Arc-hyperbolic tangent

cabriggs

alexg · Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa

RCIngham · Posted: Thu Nov 23, 2006 11:14 am **Post subject:**

alexg · Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa

tessitd · Senior Joined: Sep 05, 2006 Posts: 286 Location: Colorado

Thanks for all that replied. I will look into the Verilog 2005 library, does VCS 2006.06 have support?

Regarding modelling - what I was really after was injecting noise into an algorithm. One class of noise is of course random. But this design also has anti-aliasing which is sensitive to a slow moving sin wave. So we wanted to create this as one of our noise sources.

But I didn't find a math package in SV or in Verilog 2001. I will review what is in Verilog 2005 if VCS supports it. Also using the C math package is very doable. I just found this lack of math package to be an issue.

For RCIngham I am a big fan of the VHDL IEEE math_real package Smile

I wish that SV would adopt some of these better features of VHDL!

TomT...

shalom · Posted: Wed Nov 29, 2006 6:58 am **Post subject:**

The IEEE SV standard 1800-2005 includes Verilog-2005. 1800 is a set of extensions to Verilog-2005.

However, in practice, at the current time, many tools implement older versions of SV.

Even the tools which are implementing the IEEE version of SV have not yet implemented many of the extensions to Verilog-2001 which are defined in the Verilog-2005 standard.

So in principle, SV includes Verilog-2005. In practice, actual implementations do not yet do this.

tessitd · Senior Joined: Sep 05, 2006 Posts: 286 Location: Colorado

DavidCastle · Posted: Wed Oct 08, 2008 3:19 pm **Post subject:**

4 years

DavidCastle · Posted: Wed Oct 08, 2008 3:36 pm **Post subject:**

Seriously section 17 defines a lot more system tasks and functions in 2005 than 2001.

But, where in the SystemVerilog LRM does it specifically say that Verilog system tasks and functions are supported?

dave_59 · Posted: Wed Oct 08, 2008 4:54 pm **Post subject:**

DavidCastle · Posted: Wed Oct 08, 2008 5:04 pm **Post subject:**

Greetings Dave,

I saw that statement, but it sounds so nebulous that I didn't think it was really saying what it sounded like. And, it leaves a lot unsaid like, "Which version is an extension of which version?"

Regards,
David

tessitd · Senior Joined: Sep 05, 2006 Posts: 286 Location: Colorado

Ok,

So I am using VCS and I put in my code:

mylog = $sin(.5);

The compiler throws a message like it doesn't understand $sin? What am I missing?

TomT...