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rmalvi
Senior
Joined: May 23, 2006
Posts: 11
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 Posted: Sat Oct 21, 2006 4:09 am Post subject: File IO library in System Verilog? |
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Hi,
Isnt there a good library to read and operate on files in SystemVerilog? Or are the $readmem functions from Verilog the only supported methods? I searched for this but could not find anything but the $readmem functions.
Thanks.
Regards,
Rahul |
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Janick
Site Admin
Joined: Nov 29, 2003
Posts: 1382
Location: Ottawa, ON Canada
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| Posted: Sat Oct 21, 2006 9:09 am Post subject: |
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| The functions you are looking for are specified in 1364-2001 LRM, Chatper 17. SystemVerilog is an add-on to Verilog 2001. |
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chrisspear
Senior
Joined: Jun 15, 2004
Posts: 202
Location: Marlboro, MA
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| Posted: Fri Oct 27, 2006 11:51 am Post subject: |
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The Verilog-2001 standard added a set of system tasks that parallel the C stdio library: $fgetc, $fgets, $fscanf, etc. The 1384 spec added $feof.
For best results, use the SystemVerilog string type with these tasks. The original tasks were defined to work with the Verilog reg, a low level data type that has problems with character alignment.
I just wrote a function to read a set of C #define statements into an associative array with a string index, and the file I/O tasks worked great. Here is a snippet for your reference:
| Code: | `define EOF 32'hFFFF_FFFF
module read_pattern;
string params[string], s;
initial begin
get_values("c_ov_defines.def");
foreach (params[s])
$display("params[%s] = 0x%h / %d.", s, params[s], params[s]);
end // initial
function void get_values(string fname) ;
integer file, c, r, value;
string sname, sval, sv;
file = $fopen(fname, "r");
if (!file) // If error opening file
return; // Just quit
while (!$feof(file)) begin
c = $fgetc(file);
/* Check the first character for comment */
if (c == "/")
r = $fgets(sname, file);
else if (c != 10)
begin
// Push the character back to the file then read the next line
r = $ungetc(c, file);
r = $fscanf(file," #define %s %s", sname, sval);
sv = sval.toupper;
//$display("#define %s %s", sname, sv);
// check to see if form is of 0X123_FED
if (sv.substr(0, 1) == "0X")
begin
sv = sv.substr(2,sv.len()-1);
value = sv.atohex();
end
else
begin
// Format is 32'h1234_ABCD
// Skip over width
r = 0;
while (sv.substr(r,r) >= "0" && sv.substr(r,r) <= "9")
r++;
sv = sv.substr(r, sv.len()-1);
if (sv.substr(0,0) != "'") begin
$display("Expecting ' in <%s> >%s<", sv, sval);
return;
end
if (sv.substr(1,1) == "H")
begin
sv = sv.substr(2, sv.len()-1);
value = sv.atohex();
end
else
begin
sv = sv.substr(2, sv.len()-1);
value = sv.atoi();
end
end // else: !if(sv.substr(0, 1) == "0X")
// $display("sval=%s, value=0x%h/%0d.", sval, value, value);
params[sname] = value;
end
end // while not EOF
$fclose(file);
endfunction
endmodule // read_pattern
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This can read in the following file:
| Code: |
// comment
#define ADDR_1 16'h0001
#define ADDR_5 16'h0005
#define ADDR_11 16'h000B
#define ADDR_F 160'HF
#define ADDR_A 0xa
#define ADDR_C 0XC
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_________________
Chris Spear
Co-Author: SystemVerilog for Verification - 3rd edition!
http://chris.spear.net/systemverilog |
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