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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 51 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Learning Tool: PSL expression to English Translator          Verification Guild Forum Index -> Assertions View previous topic :: View next topic   Author Message SAHO Senior Joined: Oct 16, 2004 Posts: 24 Posted: Sun Nov 07, 2004 7:14 am    Post subject: Learning Tool: PSL expression to English Translator Is there any tool that takes in PSL property and translates into something like below. Code: assert (a -> b) has the following behaviour if a is TRUE, b will be checked. if b is also TRUE, the assertion HOLDS. if b is FALSE, the assertion FAILS. if a is FALSE, the assertions HOLDS. PSL LRM Reference is XXX SAHO Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Sun Nov 07, 2004 3:26 pm    Post subject: Re: Learning Tool: PSL expression to English Translator SAHO wrote: Is there any tool that takes in PSL property and translates into something like below. Code: assert (a -> b) has the following behaviour if a is TRUE, b will be checked. if b is also TRUE, the assertion HOLDS. if b is FALSE, the assertion FAILS. if a is FALSE, the assertions HOLDS. PSL LRM Reference is XXX SAHO Hi Saho, As you will soon realize, any complex/non-trivial assertion/property/sequence will be too complex to express in a natural language (such as English) without ambiguity. What you are looking for is a way to "visualize" your PSL/SVA. As part of our upcoming SVA book we address this issue. Though many vendors are working on this idea, I read that @HDL has a product named "Assertion Studio" that does some thing close to it. HTH, Ajeetha _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top SAHO Senior Joined: Oct 16, 2004 Posts: 24 Posted: Sun Nov 07, 2004 5:37 pm    Post subject: Ajeetha Quote: What you are looking for is a way to "visualize" your PSL/SVA. I bet this can be VERY useful indeed when a new engineer just has been given a PSL task to do. On the Doulos PSL Golden Reference (i am NOT being paid by Doulos in any way ), timing diagram for most PSL constructs are clearly shown. Quote: As part of our upcoming SVA book we address this issue. When the book is due for public release? Any prediction? Is it possible for you to elaborate this issue further as it is very intriguing to me. SAHO Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1237 Location: Los Angeles, CA Posted: Tue Nov 09, 2004 9:49 pm    Post subject: Quote: When the book is due for public release? Any prediction? The book "SystemVerilog Assertions Handbook … for Formal and Dynamic Verification" by Ben Cohen, Srinivasan Venkataramanan, and Ajeetha Kumari is expected to be released on Dec 10, 2004, and is currently undergoing the printing process. Information about the book can be obtained from http://www.abv-sva.org/sva_preface.pdf We are very excited about this book because it provides very pragmatic information on SystemVerilog Assertions language and applications throughout the design process, from requirements thru design and verification. Please read the TOC, forewords, and preface to get more information about the contents of the book, and how ABV is highly recommended as a documentation and verification methodology. Quote: What you are looking for is a way to "visualize" your PSL/SVA. Is it possible for you to elaborate this issue further as it is very intriguing to me. Check out this link on this topic: http://www.systemverilog.org/pdf/AT_HDL_Symposium.pdf Ben Cohen _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Assertions All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You can post new topics in this forum You can reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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