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You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Question : Know - How on implementing smart testbench          Verification Guild Forum Index -> Simulation View previous topic :: View next topic   Author Message SAHO Senior Joined: Oct 16, 2004 Posts: 24 Posted: Fri Oct 29, 2004 1:23 pm    Post subject: Question : Know - How on implementing smart testbench Hello experts in functional verification: I would like to know if there are example codes that clearly illustrating smart VHDL testbench that introduces: - 1) constrained pseudo random testing. Most of my testcase use the direct-test methodology, implemented using TCL macro scripts which set up testbench's VHDL generics to different desired values in order to stimulate different part of DUT. I would like to hear your thoughts and experience. regards, SAHO Back to top Janick Site Admin Joined: Nov 29, 2003 Posts: 1382 Location: Ottawa, ON Canada Posted: Fri Oct 29, 2004 2:11 pm    Post subject: Re: Question : Know - How on implementing smart testbench SAHO wrote: smart VHDL testbench that introduces: - 1) constrained pseudo random testing. You can't do that in VHDL. You have to use a Hardware Verification Language for that. Oh, there are random number generation packages in VHDL - but you need a full-blown constraint solver with declarative constraints to truly implement constrained stimulus. Back to top asif Senior Joined: Oct 20, 2004 Posts: 18 Posted: Sat Oct 30, 2004 7:12 am    Post subject: Although smart testbenches should be highly independent of languages and give user flexibility to re-use and add more features easily. I still consider VHDL not very much suitable for building good verification environments . I believe currently there is no single language that can give a smartest test bench or best features for test bench but a mix of all languages using best of each would be the smartest test bench. I do see the SystemVerilog as the potential candidate that bring best from all the worlds but one never knows how much vendor really support. Back to top rpaley_yid Senior Joined: Jan 14, 2004 Posts: 30 Posted: Tue Nov 02, 2004 6:29 pm    Post subject: One way to implement constrained random testing in VHDL is to use a pseudo-random number generator to generate a random number with a defined range. Use this number as the index either to an array or an enumerated type. Back to top Janick Site Admin Joined: Nov 29, 2003 Posts: 1382 Location: Ottawa, ON Canada Posted: Tue Nov 02, 2004 6:43 pm    Post subject: rpaley_yid wrote: One way to implement constrained random testing in VHDL is to use a pseudo-random number generator to generate a random number with a defined range. Use this number as the index either to an array or an enumerated type. Unfortunately, this only succeeds in constraining a single scalar value. And modifying the constraint requires modifying the generation code. How would you express and maintain more complex constraints such as "fill a packet payload with random bytes of increasing values with a sum equal to 0xFF" for two consecutive packets of random (but equal) lengths then a third packet with no payload at all and a FCS error"? or "whenever an arithmetic opcode targets a register, do not use that register in the next opcode. control flow opcodes must not be followed by another control-flow opcode for the next 3 instructions". True constrained random stimulus needs the ability to contrain multiple scalar values, in multiple dimensions. That requires a constraint solver i.e. the concurrent solving of multiple random variables and boolean equations. Oh! and if you truly are using random stimulus, then you'll need functional coverage. Another thing built in HVLs but not HDLs. Back to top rpaley_yid Senior Joined: Jan 14, 2004 Posts: 30 Posted: Thu Nov 04, 2004 3:40 pm    Post subject: Janick wrote: How would you express and maintain more complex constraints such as "fill a packet payload with random bytes of increasing values with a sum equal to 0xFF" for two consecutive packets of random (but equal) lengths then a third packet with no payload at all and a FCS error"? One way to solve this problem in VHDL is to write a file parser to read in and process the following constraints file: define_packet --num_packet 2 define_packet --length random define_packet --data --random increment define_packet --data --sum 0xFF define_packet --fcs_error false send_packet define_packet --num_packet 1 define_packet --length 0 define_packet --fcs_error true send_packet Back to top Janick Site Admin Joined: Nov 29, 2003 Posts: 1382 Location: Ottawa, ON Canada Posted: Thu Nov 04, 2004 4:45 pm    Post subject: rpaley_yid wrote: One way to solve this problem in VHDL is to write a file parser to read in and process the following constraints file: Sure. But writing the parser is the easy part. Hmmm... With STD.TEXTIO, I'm not sure it'll be that easy after all... Next, you'll have to write the solver itself. In the meantime, while you'll still be sorting the semi-colons, I'll have written: Code: class scenario {    eth_frame frames[3];   constraint basic {      frames[0].length == frames[1].length;      foreach (frames, i) {         if (i < 2) {            foreach (frames[i].data, j) {               if (j > 0) frames[i].data[j] > frames[i].data[j-1];            }            frames[i].data.sum() == 8'hFF;            frames[i].fcs == 32'h0;         }      }      frames[2].length == 0;      frames[2].fcs != 32'h0;   } } run and debug the test and moved on to the next one. Sure, you can do anything you want with VHDL, but is it the best investment of your limited time? Back to top alexg Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa Posted: Thu Nov 04, 2004 5:31 pm    Post subject: Janick wrote: How would you express and maintain more complex constraints such as "fill a packet payload with random bytes of increasing values with a sum equal to 0xFF" for two consecutive packets of random (but equal) lengths then a third packet with no payload at all and a FCS error"? It seems like it is impossible to do so The maximum of increasing byte values is: 1+2+3+4+5+6+7 = 28, or 1C. It is much smaller than any of 0xFF values. Last edited by alexg on Fri Nov 05, 2004 12:36 am; edited 1 time in total Back to top rpaley_yid Senior Joined: Jan 14, 2004 Posts: 30 Posted: Thu Nov 04, 2004 7:12 pm    Post subject: Janick wrote: Sure. But writing the parser is the easy part. Hmmm... With STD.TEXTIO, I'm not sure it'll be that easy after all... Please give me a little credit, obviously, a good string parser package is needed. One public example is Mr. Cohen's code. I also remember seeing on some university's site public VHDL implementations of C functions like printf, scanf, etc. Janick wrote: Next, you'll have to write the solver itself. In the meantime, while you'll still be sorting the semi-colons, I'll have written: Code: class scenario {    eth_frame frames[3];   constraint basic {      frames[0].length == frames[1].length;      foreach (frames, i) {         if (i < 2) {            foreach (frames[i].data, j) {               if (j > 0) frames[i].data[j] > frames[i].data[j-1];            }            frames[i].data.sum() == 8'hFF;            frames[i].fcs == 32'h0;         }      }      frames[2].length == 0;      frames[2].fcs != 32'h0;   } } run and debug the test and moved on to the next one. Sure, you can do anything you want with VHDL, but is it the best investment of your limited time? It think it is obvious that a verification environment written with an HVL can be written much faster and with less code than VHDL. However, a complex verification environment can be written in VHDL. This was the point i was trying to make. While we're on the language issue. Does anyone think VHDL-200x ( whenever it arrives ) will present a challenge to any of the other more established HVL's, including SystemC ? Back to top Janick Site Admin Joined: Nov 29, 2003 Posts: 1382 Location: Ottawa, ON Canada Posted: Fri Nov 05, 2004 1:22 pm    Post subject: alexg wrote: It seems like it is impossible to do so The maximum of increasing byte values is: 1+2+3+4+5+6+7 = 28, or 1C. It is much smaller than any of 0xFF values. Why are you limiting yourself to a 7-byte payload? And "increasing" does not mean "incrementing". Here's a solution: 0x03 + 0x05 + 0xF8 = 0xFF Also, in the case of Vera (and SystemVerilog), since they use the Verilog arithmetic model with automatic truncation, this would also be a valid solution (if the constraint expression is 8-bit wide): 0x02 + 0xFE + 0xFF Back to top alexg Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa Posted: Fri Nov 05, 2004 3:56 pm    Post subject: Quote: Why are you limiting yourself to a 7-byte payload? And "increasing" does not mean "incrementing". Sorry, you are right. Typical problem - wrong understanding of human-language written requirements. And yet another argument for importance of formal specifications... Back to top srini Senior Joined: Jan 23, 2004 Posts: 430 Location: Bengaluru, India Posted: Fri Nov 05, 2004 6:24 pm    Post subject: rpaley_yid wrote: Please give me a little credit, obviously, a good string parser package is needed. One public example is Mr. Cohen's code. I also remember seeing on some university's site public VHDL implementations of C functions like printf, scanf, etc. There is/was PCK_FIO from easics available in the web. You may be able to google it. I am sure you deserve the credit, and no one needs to really give it, you have it with you by posting a *possible* solution. I think we are looking at "feasible", better, easier ways of doing things. Sure an optimal SW can be written at ASM level, why do most of the SW guys use C/C++ etc.? Some languages are originally developed with few objectives in mind, and they fit that role the best. HDLs - VHDL/Verilog are intended for Design description/documentation, they fit best there, see the way SystemC based RTL went few years ago - a System level language trying to adapt itself to "clock cycle" accurate, synthesisable stuff. So the real point I believe is, NOT whether VHDL *can do it*, rather could better be: "Which one is more feasible". Sure there is an extra *cost* factor involved, but thanks to major EDA vendors willing to support SystemVerilog testbench capabilities, I believe that factor will become irrevant going forward. Janick wrote: In the meantime, while you'll still be sorting the semi-colons, FWIW, I would let my editor (Emacs + VHDL Mode) to do that (i.e. sorting semi-colons) for me Quote: It think it is obvious that a verification environment written with an HVL can be written much faster and with less code than VHDL. However, a complex verification environment can be written in VHDL. This was the point i was trying to make. I think your point is valid, but IMHO it is not as feasible, maintainable etc. Quote: While we're on the language issue. Does anyone think VHDL-200x ( whenever it arrives ) will present a challenge to any of the other more established HVL's, including SystemC ? I know that VHDL-TBV commitee is looking at some possibilities, but history says that VHDL standardization takes *long* time - not to mention the tool vendor implementation priorities after that. Just look at the number of years it takes to get VHPI (dual of Verilog's PLI-VPI) standardized - I do understand VHDL is far more complex and hence more complex will be any API to it, but just wanted to refer to it as one relevant example. Thanks, Srinivasan _________________ Srinivasan Venkataramanan Chief Technology Officer, CVC www.cvcblr.com A Pragmatic Approach to VMM Adoption SystemVerilog Assertions Handbook Using PSL/SUGAR 2nd Edition. Contributor: The functional verification of electronic systems Back to top srini Senior Joined: Jan 23, 2004 Posts: 430 Location: Bengaluru, India Posted: Fri Nov 05, 2004 10:57 pm    Post subject: srini wrote: So the real point I believe is, NOT whether VHDL *can do it*, rather could better be: "Which one is more feasible". Sure there is an extra *cost* factor involved, but thanks to major EDA vendors willing to support SystemVerilog testbench capabilities, I believe that factor will become irrevant going forward. Just wanted to add a small note: VCS already has this kind of capability natively built-in, it is called "Native TestBench". (Though it is not SV-TB yet). Regards, Srinivasan _________________ Srinivasan Venkataramanan Chief Technology Officer, CVC www.cvcblr.com A Pragmatic Approach to VMM Adoption SystemVerilog Assertions Handbook Using PSL/SUGAR 2nd Edition. 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