What simulator do you use?

cschalick · Posted: Tue Oct 26, 2004 9:38 am **Post subject: What simulator do you use?**

We are re-evaluating our logic simulator choice. I assume most people use VCS and/or NC, but I'd like to hear from others about your experiences.

What simulator(s) are you all using? What advantages do you see for one over another?

Thanks for any feedback.

Chris

vhdlcohen · Posted: Tue Oct 26, 2004 5:49 pm **Post subject:**

asif · Senior Joined: Oct 20, 2004 Posts: 18

The other factors for choosing the simulators are .

1.Type of design: Is it an SoC which involves integration of various IP cores etc .Then mixed language simulators are the best.

2. Size of design : Only the best simulators can with stand large size of design like VCS/NC/Modelsim.Since most of the long simulations are run in non-interactive mode(non-GUI) the GUI/waveform display has no meaning towards the end of the design cycle.

3. Multi-Processor support : I still wonder how many simulators really exploit features dual processor and 64 bit architecture.

4. OS support : All future development environment are moving towards Linux this is also become a key factor.

5. Compile/Interpreted Mode of operation : Although most of the standard simulators operate in compiled mode.

6.Stage of the design : For signoff its best to use the standard simulators whereas during initial phase of design one can go with a cheaper simulator.

However from management perspective its the how good deal can they get from the vendor Smile

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akuchlous

Perhaps this link could help you out.

http://www.deepchip.com/items/snug03-06.html

Thanks
Ankur Kuchlous

cschalick · Posted: Wed Oct 27, 2004 9:37 am **Post subject: Deepchip**

The Deepchip article is exactly on point for my question - thx for the ptr Ankur!

Chris

akuchlous · Posted: Thu Oct 28, 2004 6:24 am **Post subject: Design ...**

Cschalick

I was just curious...

So a couple of questions...
1) Is ur design verilog/vhdl/mixed?
2) what is ur design size (>10K, >1000K, >1M)?
3) Can I get any details abt the design?

As per my experiance,

I have worked on VCS in my intern, and it was pretty easy to use.

Modelsim, is good for mixed designs.

I have not had a good handle on NC ...

-Ankur

cschalick · Posted: Thu Oct 28, 2004 8:24 am **Post subject: logic simulator usage**

Our (current) environment is as follows:

- verilog only, w/C test code through PLI
- design sizes from 10k flip flops to 300k flip flops (convert as you see fit)
- various soft and hard IP
- tests run queued
- GUI only used for waveform debugging

Our designs have soft IP processors running < 1 MB of code and data running from off-chip memories and use standard communications interfaces (serial/ethernet).

Can anyone comment on price/performance between ModelSim and VCS?

Any thoughts on migrating from C/PLI to SystemC? What sort of issues might we run into there? I saw some suggestions about non-standard PLI with VCS making conversion to other simulators complicated.

Any issues with IP support with ModelSim?

Feedback appreciated,
Chris

bugfinder · Senior Joined: Jan 12, 2004 Posts: 19

IMHO.
For vhdl designs, Modelsim provides excellent GUI supports which makes debugging easy and faster. From my experience, it is quite stable for even large designs(running upto 5 M gates).
For Verilog mixed with VHDL designs, Modelsim is again stable. All C testing has to be done thru PLIs earlier which has its impact on the performance. Now, SystemC is natively supported by Modelsim(ofcourse for a few extra $$$) which means in my view, C code needs to be converted into SystemC and used(I would request some experienced guys to comment on this, I have not done this ).

So far, for Vhdl designs, VCS (actually scirocco and its predecessor), lacked few features and GUI was not that good. But the new VCS-MX seems to solve those problems. I have not tried it yet.
But for verilog designs, it offers some goodies. The new system verilog (which is naturally the next step for verilog users) is natively supported by VCS-MX which means the testbenches written using systemverilog could run much faster without the performance effect of PLIs. I dont know much about systemC support in VCS.

In both the above cases, I dont think the batch mode runs will give any significant perfomance difference.

I have not used NCSIM...

Another important decision which one needs tomake for long term commitment is, which Assertion language one is going to choose? Modelsim currently supports PSL(That comes with extra license and $$$). VCS-MX will support only SVA(part of sytemverilog support). This factor should also be taken into consideration.

"Remember Frost!! Two Roads Diverged into the woods and I took the one least travelled by ...."

Good Luck !!

vhdlcohen · Posted: Fri Oct 29, 2004 6:49 am **Post subject:**