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Verification Guild: Forums |
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Anoop
Senior
Joined: Sep 29, 2004
Posts: 10
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 Posted: Tue Oct 19, 2004 8:29 am Post subject: Co - Verification |
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| I'm new to the field of co-verification.please suggest a few tools on coverification. |
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asif
Senior
Joined: Oct 20, 2004
Posts: 18
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| Posted: Wed Oct 20, 2004 12:57 am Post subject: Co-Verification |
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Mentor has a tool called "Seamless" that can be used for co-verification.Cadence tool is called Virtul Component Co-design(VCC) and i remember there was tool from Synosys long time back called Eaglei ,i wonder if it stil exists.
-Asif |
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alain94040
Senior
Joined: Jun 03, 2004
Posts: 22
Location: San Jose
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| Posted: Wed Oct 20, 2004 3:09 pm Post subject: Re: Co - Verification |
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| Anoop wrote: | | I'm new to the field of co-verification.please suggest a few tools on coverification. |
If by co-verification you hardware/software co-verification, there are quite a few solutions out there, with different tradeoffs.
It's quite simple really:
To simulate software, you have two basic options: use an instruction set simulator (ISS), which is a C program that simulates the processor running your software at the instruction level. It's fast (millions of instructions per second), but viewed from the hardware perspective, it's not 100% cycle accurate. Or use the actual processor, or a hardware representation of it.
To simulate hardware (RTL) in a completely cycle-accurate fashion, you can use a Verilog simulator such as VCS, NC or ModelSim which will give you thousands of cycles per second, or if you care about speed, use hardware assistance to "emulate" the RTL at millions of cycles per second. The second approach is to have software (C/C++) models of your hardware design. This is where the word "transaction" usually comes in: instead of looking at buses cycle by cycle, you exchange higher-level information between various components. That will give you the speed (MIPS), but you lose in accuracy. And of course, there is the issue of who writes the models and how close to the actual Verilog RTL they are.
That's it for the theory. Now, when you combine those different options, you get a bunch of commercial tools:
Seamless: uses an ISS talking to a Verilog simulator - really useful to debug the RTL with some known software driver code
Virtio : uses an ISS talking to a high-level model of the hardware - really useful to get an early start on developing non-hardware-critical application software
ZeBu: uses hardware assistance for both the processor and hardware model - really useful to debug drivers and any piece of software whose interaction with the hardware is critical
Alain Raynaud
Technical Director, EVE-USA |
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jra
Junior
Joined: Aug 27, 2004
Posts: 5
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| Posted: Fri Oct 22, 2004 3:03 am Post subject: |
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Instead of looking for tools, you can learn more about it then decide what kind of tools make sense for you.
I have written a book on co-verification that is a good place to start.
http://coverification.home.comcast.net
or just search for co-verification on Amazon and you will find it.
Regards,
Jason |
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alexg
Senior
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Joined: Jan 07, 2004
Posts: 586
Location: Ottawa
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| Posted: Mon Oct 25, 2004 8:30 am Post subject: |
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| Quote: | | A debug environment that handles multiple ISS models and RTL blocks. The RTL simulator converts to cycle-based 2-state models providing upto 100 times speed increase. |
There is a good paper about 2-state simulation perfomance (Cliff Cummings , SNUG 2004):
http://www.sunburst-design.com/papers/CummingsSNUG2004Boston_2StateSims.pdf
In his opinion, speed increase using 2-state simulators is significantly smaller, comparing to recent (not outdated) simulators.
| Clifford Cummings wrote: | | In the early 1990’s, this HP in-house RTL Verilog simulator was 20X-80X faster than vendor simulators, but by the later 1990’s it was only 0.8X - 2.3X faster than commercial tools, so commercial tools largely replaced in-house simulators. |
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Janick
Site Admin
Joined: Nov 29, 2003
Posts: 1382
Location: Ottawa, ON Canada
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| Posted: Mon Oct 25, 2004 10:10 am Post subject: |
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| cor wrote: | | Well, we understand these problems and have implement it properly, resulting in a signifcant speedup |
Any whitepapers, customer stories or results from actual experiments to backup these claims?
Please keep the content factual and technical. Unsubstantiated marketing claims will be moved to the "EDA News" forum. |
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Anoop
Senior
Joined: Sep 29, 2004
Posts: 10
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| Posted: Tue Oct 26, 2004 4:40 am Post subject: Summit Design - Virtual CPU |
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| I thank everyone for their suggestions, but can i have some facts about the tool Summit Design - Virtual CPU as i need to use this tool. |
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