stimulus vector generation

thebamaman · Newbie Joined: Oct 11, 2004 Posts: 3

I am curious about people's approaches for stimulus generation. Currently (hopefully not for much longer) our block-level testing uses a model written in C that is used to compare against the RTL. The RTL acts as a black-box that is driven by the same stimulus that is sent to the C model, and then the outputs of both are compared. Now that you have an idea of our environment, here are the usual tests written to stimulate the model and RTL.

I was wondering about the best way to go generating stimulus. Are the walking tests that necessary anymore? Are directed stimulus tests, then random tests any better or worse than constrained random testing? Conceptually the directed stimulus tests usually take quite a bit of time to write, and it seems like directed random tests could take less time, but is that correct? I'm trying to shore up our verification strategies, so all input is greatly appreciated.

jmcneal · Posted: Tue Oct 19, 2004 11:07 am **Post subject:**

From my experience the walking 1's and A's 5's are mostly used in memory testing. They are often used in production testing to test for manufacturing errors (not functional errors).

These are the types of tests that get written in directed environments that are intended to demonstrate that the block is good enough with a minimum number of tests. Since each test case takes the same effort to write, the number of cases is usually reduced as much as possible, to save schedule time.

If it were me, I'd write a random stimulus generator and start that running. Then I'd write coverage points for the corner cases the designer has asked for. Writing and reading random data for any significant period of time should easily demonstrate correct functionality better than walking 1's and 0's. If it is necessary to have the walking 1's, 0's, A's, 5's, then adding that (as a constraint or as coverage) is usually fairly simple.

In many cases good a random stimulus test may take longer than a directed test, but the good random test case will simulate lots of different combinations, while the directed test will only test one thing. Let the random case run long enough and you will hit the walking 1s, 0s, As, and 5s. As well as the 0F's, the 33's, etc.

j

Marcus · Newbie Joined: Sep 09, 2004 Posts: 4

As far as walking ones/zeroes are concerned, they are essential in integration testing. Think, for instance, of a block with a memory-like (address, data) interface that will be accessed by more than one other block. You want to make sure they are hooked up correctly. If you deal with address decoders (register files in RTL components, bus-switches, etc.) you want to make sure that there is no crosstalk (caused by functional address decoding errors). This requires writing/reading all locations in both, ascending and descending direction, depending where you start painting the boxes in black. Devices with large address ranges (e.g. switches), need to be dealt with differently though. Typically these devices have some sort of enable signal at each port which could be verified by an appropriate assertion.

As for random vs. directed, I'd strongly recommend looking into random testing. But keep in mind that you want to cut down simulation time by writing constraints for potential rat holes you know of up front. There is no point in waiting for a random generator to come up with a sequence that is quickly written as directed test (or a set of strong constraints for that matter). You don't have time to waste, do you.

Best regards,
Marcus

asif · Senior Joined: Oct 20, 2004 Posts: 18

Walking ones,zeros and A5 : These are very much useful for register testing as well. Generally the first release of RTL has lots of unconnected registers and these test help in checking the connections.
Later during the project ie end of verification they add for code-coverage metric.

Directed stimulus for block : These ensure that the intended functionality is implemented. For functional verification this takes about 85% of the time.Foucs only on requirments here.

Random stimulus : Once your done with directed tests and sure that functionality is well tested. Give random vectors. The results can be shocking at times..

Corner cases by RTL designer : Assertions can be of very much help here.Ensure you have hit the condition asked by the designer. Otherwise a corner case is a subset of random test.

Well there is no best way of generating stimulus but step and step way of doing is best Smile

When using the reference model based approach the stimulus "may not look very useful " as C and RTL outputs are directly compared But are still "required/must" because

1.The C model would take some time for development.

2.The C model has to be cycle accurate.

3.The reference C model has to be tested well.

Using a reference C model gives additional confidence but one still needs to run all the above tests.

-Asif