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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 41 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Auto variables in procedural concurrent assertions          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message ashishd Junior Joined: Dec 09, 2008 Posts: 6 Posted: Wed May 09, 2012 12:07 am    Post subject: Auto variables in procedural concurrent assertions Hi, Can I use automatic variables in a concurrent assertions written in an always block? Here's a snippet on the same: property prop(arg1, arg2); arg1 -> arg2 endproperty always begin automatic int a; int b; a1 : assert property (a,b); else ...... end VCS shouts for an error when I try to pass a as an argument in the assertion. From LRM, I could not conclude that only static variable needs to be passed. Any inputs? PS: I know the property does not make a sense but this is just for the sake of explanation. Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1248 Location: Los Angeles, CA Posted: Wed May 09, 2012 10:41 am    Post subject: Re: Auto variables in procedural concurrent assertions ashishd wrote: Can I use automatic variables in a concurrent assertions written in an always block? Yes. Per LRM on "sampling" SV_LRM wrote: --Sampled values of automatic variables (see 16.14.6), local variables (see 16.10), and active free checker variables (see 17.7.2) are their current values. — When a past or a future value of an automatic variable is referenced by a sampled value function,the current value of the automatic variable is taken instead. Here is test code for use of automatic variable. Note tht one of the biggest use of automatic variable is in loops for determining an index. Code: module autovar;     bit clk, x, y;     bit[0:4] v=5'b10101;     int w=1, q=1110, m=4;     initial forever #10 clk=!clk;     default clocking cb_clk @ (posedge clk);  endclocking     property prop(arg1, arg2);         (arg1>0) ##1 (arg2 <100);      endproperty     always_ff @ (posedge clk)  begin : aly         automatic int a;         int b;         a=m; b=50;         $display("at t=%t  a=%d, b=%d", $time, a, b);         ap_auto1 : assert property (prop(a,b)) else $display("ap_auto1: at t=%t  sampled_a=%d, a=%d", $time, $sampled(a), a);          ap_static1 : assert property(prop(w,q));          m<=m-1;                for (int i=0; i<5; i++) begin : lp1             ap_auto_loop:  assert property(i<5 ##1 v[i] );             ap_const_loop: assert property(const'(i)<5 ##1 v[const'(i)] );         end : lp1     end  : aly     initial begin         repeat(3) @ (posedge clk);         q <= 5;         @ (posedge clk) q<=1000;         // aly.a = 4; ///Hierarchical access to item a in automatic function (aly) not allowed     end endmodule : autovar _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top ashishd Junior Joined: Dec 09, 2008 Posts: 6 Posted: Wed May 09, 2012 11:18 am    Post subject: again compilation error Thanks Ben for prompt response. Even I expected that automatic variables should work. And I have written my code pretty much in the same way as your example. However, I have now developed a very small demo program to demonstrate what I am doing. And I am getting the compilation error in that. Here is the "exact" program module test; property prop (a,b); a -> b; endproperty bit clk; always @(posedge clk) begin automatic int c,d; assert property ( prop(c,d)) else $display("HELLO"); end endmodule And the output that I get: Error-[SV-IRTAV] Illegal reference to automatic variable procedural_assertion.sv, 9 "test.0.c" Hierarchical reference to automatic variable 'c' is not legal. Error-[SV-IRTAV] Illegal reference to automatic variable procedural_assertion.sv, 9 "test.0.d" Hierarchical reference to automatic variable 'd' is not legal. Error-[SV-IRTAV] Illegal reference to automatic variable procedural_assertion.sv, 9 "test.0.d" Hierarchical reference to automatic variable 'd' is not legal. Error-[SV-IRTAV] Illegal reference to automatic variable procedural_assertion.sv, 9 "test.0.c" Hierarchical reference to automatic variable 'c' is not legal. 4 errors CPU time: .037 seconds to compile I admit this does not make sense but it does not even compile. And the same error I am facing in my original assertion code. I am using VCS and tried with 2009 and 2012 versions but the same output. Any idea what I am doing wrong? Or a tool issue? Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1248 Location: Los Angeles, CA Posted: Wed May 09, 2012 11:47 am    Post subject: Re: again compilation error If you look at my example, initial begin aly.a = 4; ///Hierarchical access to item a in automatic function (aly) not allowed One way for your code to work in VCS is to const cast the automatic variable. Thus: Code: module test;   property prop (a,b);     a -> b;   endproperty   bit clk;   always @(posedge clk) begin     automatic int c,d;     assert property ( prop(const'(c), const'(d)))     else       $display("HELLO");   end endmodule  I don't have my simulator on this current machine. Try it and let me know. That should work. _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top ashishd Junior Joined: Dec 09, 2008 Posts: 6 Posted: Wed May 09, 2012 11:54 am    Post subject: I had tried it earlier as well and it did not work. However, I checked it again as per your suggestion and here's what I get: "System Verilog keyword const' is not expected to be used in this context". Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Wed May 09, 2012 1:17 pm    Post subject: ashishd wrote: I had tried it earlier as well and it did not work. However, I checked it again as per your suggestion and here's what I get: "System Verilog keyword const' is not expected to be used in this context". As far as I recall, automatic variables are not allowed to have "persistence" and hence are disallowed in assertions. Ben - does your code run in a tool? It failed to do so in 1 tool on my end (and VCS as per the other poster). Ajeetha, CVC www.cvcblr.com/blog _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1248 Location: Los Angeles, CA Posted: Wed May 09, 2012 1:41 pm    Post subject: Ajeetha wrote: ashishd wrote: I had tried it earlier as well and it did not work. However, I checked it again as per your suggestion and here's what I get: "System Verilog keyword const' is not expected to be used in this context". As far as I recall, automatic variables are not allowed to have "persistence" and hence are disallowed in assertions. Ben - does your code run in a tool? It failed to do so in 1 tool on my end (and VCS as per the other poster). Ajeetha, CVC www.cvcblr.com/blog regarding sampling of variables, the 2009 LRM states in 16.6.2: “The variables that can appear in expressions shall be static design variables, …” This is being changed in SystemVerilog'2012. The following code ran OK on Questa Code: always @(posedge clk) begin         automatic int c,d;         ap_cst: assert property ( prop(const'(c), const'(d)))             else                 $display("HELLO");     end // Sim results (same code as my original + the one above)  at t=                  10  a=          4, b=         50 # HELLO # at t=                  30  a=          3, b=         50 # HELLO # ** Error: Assertion error. #    Time: 30 ns Started: 10 ns  Scope: autovar.aly.ap_static1 File: autovar.sv Line: 18 Expr: q<100 # ** Error: Assertion error. #    Time: 30 ns Started: 10 ns  Scope: autovar.aly.#anonblk#0#20#4#.lp1.ap_auto_loop File: autovar.sv Line: 21 Expr: v[const'(i)] #    Local vars : const'(i) = 1   Code is at SystemVerilog.us/autovar.sv _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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