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sg8 Newbie


Joined: Apr 17, 2012 Posts: 2
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Posted: Tue Apr 17, 2012 6:54 am Post subject: Clocking blocks in generate statement |
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I have an interface which is having N number of clock inputs, here N is a parameter.
So I tried writing clocking block inside generate statement
| Code: | logic data_in[N];
logic data_out[N];
genvar i;
generate
for (i=0; i<N; i++)
begin:driver_cb
clocking m_driver_cb @ (posedge clk[i]);
default input #1 output #1;
output
data_in[i];
input
data_out[i];
endclocking : m_driver_cb
end
endgenerate
| when I tried accessing interface signal from driver class like below
| Code: | | temp_data[i] <= pin_if.driver_cb[i].m_driver_cb.data_out[i]; |
I am getting error like | Quote: | | Could not find member 'driver_cb’ in pin_if. |
So, can we use clocking blocks inside generate statement? If yes what is the problem in driver statement.
If no what is the best method to deal this problem.
Also I am having syntax error when I am using data_in[i] inside the clocking block. no error if i used only data_in
Thanks,
sg8 |
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dave_59 Senior


Joined: Jun 22, 2004 Posts: 974 Location: Fremont, CA
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Posted: Tue Apr 17, 2012 1:09 pm Post subject: |
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There are several problems in the way you are trying to use a clocking block with a generate loop.
The biggest problem is that you are not allowed to access generated block names with a variable index. So any reference to driver_cb[i] is not legal when i is a variable. It must be a genvar variable or a parameter that results in a constant expression. This is probably a showstopper fr trying to use a clocking block with an array of clocks.
The syntax problem is simple to fix, but will not help the first problem. You are only allowed to list simple identifiers as input or outputs of the clocking block. You could do | Code: | for (i=0; i<N; i++)
begin:driver_cb
clocking m_driver_cb @ (posedge clk[i]);
default input #1 output #1;
output
din = data_in[i];
input
dout = data_out[i];
endclocking : m_driver_cb |
and then you refer to driver_cb[i].m_driver_cb.din
Dave Rich
Mentor Graphics |
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Ajeetha Senior


Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India
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Posted: Tue Apr 17, 2012 10:18 pm Post subject: |
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Adding further to Dave's thoughtful language reply, your best bet would perhaps be use generate-interface combination. i.e. define your interface per-bit/lane and declare an array of them via generate. Something like:
| Code: |
interface if_per_lane (input clk);
logic data_in;
logic data_out;
clocking m_driver_cb @ (posedge clk);
default input #1 output #1;
output
data_in;
input
data_out;
endclocking : m_driver_cb
endinterface
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Then generate this interface N times.
Does that help?
Regards
Ajeetha, CVC
www.cvcblr.com/blog _________________ Ajeetha Kumari,
CVC Pvt Ltd. http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar |
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sg8 Newbie


Joined: Apr 17, 2012 Posts: 2
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Posted: Wed Apr 18, 2012 12:05 am Post subject: |
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Thanks Dave & Ajeetha,
Interface has got more signals(other clock& data signals), the code shown here is simplified and all data inputs to DUT are driven by a driver. Only clk, data_in & data_out signals are parameterized here.
Using generate-interface combination will split up interface to many & I need to pass multiple interfaces to a driver or I need to have N drivers for N interfaces. |
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