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    Verification Guild :: View topic - compatibility problem in Questasim 6.4c
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    compatibility problem in Questasim 6.4c

     
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    Author Message
    raghava216
    Senior
    Senior


    Joined: Feb 24, 2012
    Posts: 12

    PostPosted: Fri Feb 24, 2012 1:54 am    Post subject: compatibility problem in Questasim 6.4c Reply with quote

    Dear Sir,

    I wrote a controller design in vhdl and tested it with a script based test bench in Modelsim 6.0 SE.

    When I run the test case 1, it got successfully executed and generated the required report files.

    I get the following message on screen (in Modelsim 6.0 SE)

    Code:
    # -----  COMPILING  RTL and TB  MODULES FOR FUNCTIONAL SIMULATION ------
    # D:/Projects/controller
    # reading modelsim.ini
    # Modifying modelsim.ini
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity add_mod_encoder
    # -- Compiling architecture rtl of add_mod_encoder
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity trans_timeout_timer
    # -- Compiling architecture rtl of trans_timeout_timer
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity bbsy_gen
    # -- Compiling architecture rtl of bbsy_gen
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity buffer_cntr
    # -- Compiling architecture rtl of buffer_cntr
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity fair_time_out
    # -- Compiling architecture rtl of fair_time_out
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity con_sig_trans
    # -- Compiling architecture rtl of con_sig_trans
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity sys_clk_divider
    # -- Compiling architecture rtl of sys_clk_divider
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity ctrl_reg1
    # -- Compiling architecture rtl of ctrl_reg1
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity ctrl_reg2
    # -- Compiling architecture rtl of ctrl_reg2
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity std_bus_arbiter
    # -- Compiling architecture rtl of std_bus_arbiter
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity std_bus_releaser
    # -- Compiling architecture rtl of std_bus_releaser
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity std_bus_requester
    # -- Compiling architecture rtl of std_bus_requester
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity interrupt_controller
    # -- Compiling architecture rtl of interrupt_controller
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity rst_logic
    # -- Compiling architecture rtl of rst_logic
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top1
    # -- Compiling architecture rtl of controller_top1
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top2
    # -- Compiling architecture rtl of controller_top2
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top
    # -- Compiling architecture rtl of controller_top
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package textio
    # -- Compiling package io_utils
    # -- Compiling package body io_utils
    # -- Loading package io_utils
    # -- Compiling entity test
    # -- Loading package io_utils
    # -- Compiling architecture hex_test of test
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package std_iopak
    # -- Loading package io_utils
    # -- Compiling package std_tb_pkg
    # -- Compiling package body std_tb_pkg
    # -- Loading package std_tb_pkg
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package textio
    # -- Loading package std_iopak
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Loading package std_tb_pkg
    # -- Compiling entity cmd_intr
    # -- Compiling architecture bhv of cmd_intr
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity std_emulator
    # -- Compiling architecture behavioral of std_emulator
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity local_interrupter
    # -- Compiling architecture behavioral of local_interrupter
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity mc_emulator
    # -- Compiling architecture behave of mc_emulator
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity clk_gen
    # -- Compiling architecture behave of clk_gen
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_245
    # -- Compiling architecture behave of logic_245
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_a
    # -- Compiling architecture behave of logic_543_a
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_d8
    # -- Compiling architecture behave of logic_543_d8
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_d16
    # -- Compiling architecture behave of logic_543_d16
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity data_buffer
    # -- Compiling architecture behave of data_buffer
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity buffer_cntrl_analyser
    # -- Compiling architecture behave of buffer_cntrl_analyser
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity tb_top
    # -- Compiling architecture behave of tb_top
    # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity int_top
    # -- Compiling architecture behave of int_top
    # 0
    # Reading filenames from D:/Projects/controller/code/tb/sim/design_tc.txt
    # Running Test Case  :  tc_ctrl_01
    # vsim -coverage -t ps work.int_top
    # Loading D:\Modeltech_6.0\win32/../std.standard
    # Loading D:\Modeltech_6.0\win32/../ieee.std_logic_1164(body)
    # Loading D:\Modeltech_6.0\win32/../ieee.std_logic_arith(body)
    # Loading D:\Modeltech_6.0\win32/../ieee.std_logic_unsigned(body)
    # Loading work.int_top(behave)
    # Loading work.controller_top(rtl)
    # Loading work.controller_top1(rtl)
    # Loading work.sys_clk_divider(rtl)
    # Loading work.rst_logic(rtl)
    # Loading work.fair_time_out(rtl)
    # Loading work.std_bus_arbiter(rtl)
    # Loading work.bbsy_gen(rtl)
    # Loading work.trans_timeout_timer(rtl)
    # Loading work.std_bus_releaser(rtl)
    # Loading work.add_mod_encoder(rtl)
    # Loading work.std_bus_requester(rtl)
    # Loading work.buffer_cntr(rtl)
    # Loading work.ctrl_reg1(rtl)
    # Loading work.con_sig_trans(rtl)
    # Loading work.controller_top2(rtl)
    # Loading work.interrupt_controller(rtl)
    # Loading work.ctrl_reg2(rtl)
    # Loading work.tb_top(behave)
    # Loading work.clk_gen(behave)
    # Loading D:\Modeltech_6.0\win32/../std.textio(body)
    # Loading D:\Modeltech_6.0\win32/../std_developerskit.std_iopak(body)
    # Loading D:\Modeltech_6.0\win32/../ieee.std_logic_textio(body)
    # Loading work.io_utils(body)
    # Loading work.std_tb_pkg(body)
    # Loading work.cmd_intr(bhv)
    # Loading work.mc_emulator(behave)
    # Loading work.std_emulator(behavioral)
    # Loading work.buffer_cntrl_analyser(behave)
    # Loading work.local_interrupter(behavioral)
    # Loading work.logic_543_a(behave)
    # Loading work.data_buffer(behave)
    # Loading work.logic_245(behave)
    # Loading work.logic_543_d16(behave)
    # Loading work.logic_543_d8(behave)
    # ** Failure: Simulation Finished
    #    Time: 51480 ns  Iteration: 1  Process: /int_top/tb_top_i/mc_emulator_i/report_gen File: D:/projects/controller/code/tb/src/mc_emulator.vhd
    # Break at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # tc_ctrl_01 Test Case Completed at Time : 51480000 ns


    I wanted to simulate the same design with the same script based test bench in Questasim 6.4c, but I am not successful in doing so. I get the following message and the reports are not getting generated.

    Code:
    # -----  COMPILING  RTL and TB  MODULES FOR FUNCTIONAL SIMULATION ------
    # D:/Projects/controller
    # reading modelsim.ini
    # Modifying modelsim.ini
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity add_mod_encoder
    # -- Compiling architecture rtl of add_mod_encoder
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity trans_timeout_timer
    # -- Compiling architecture rtl of trans_timeout_timer
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity bbsy_gen
    # -- Compiling architecture rtl of bbsy_gen
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity buffer_cntr
    # -- Compiling architecture rtl of buffer_cntr
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity fair_time_out
    # -- Compiling architecture rtl of fair_time_out
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity con_sig_trans
    # -- Compiling architecture rtl of con_sig_trans
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity sys_clk_divider
    # -- Compiling architecture rtl of sys_clk_divider
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity ctrl_reg1
    # -- Compiling architecture rtl of ctrl_reg1
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity ctrl_reg2
    # -- Compiling architecture rtl of ctrl_reg2
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity std_bus_arbiter
    # -- Compiling architecture rtl of std_bus_arbiter
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity std_bus_releaser
    # -- Compiling architecture rtl of std_bus_releaser
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity std_bus_requester
    # -- Compiling architecture rtl of std_bus_requester
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity interrupt_controller
    # -- Compiling architecture rtl of interrupt_controller
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity rst_logic
    # -- Compiling architecture rtl of rst_logic
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top1
    # -- Compiling architecture rtl of controller_top1
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top2
    # -- Compiling architecture rtl of controller_top2
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top
    # -- Compiling architecture rtl of controller_top
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package textio
    # -- Compiling package io_utils
    # -- Compiling package body io_utils
    # -- Loading package io_utils
    # -- Compiling entity test
    # -- Loading package io_utils
    # -- Compiling architecture hex_test of test
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package std_iopak
    # -- Loading package io_utils
    # -- Compiling package std_tb_pkg
    # -- Compiling package body std_tb_pkg
    # -- Loading package std_tb_pkg
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package textio
    # -- Loading package std_iopak
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Loading package std_tb_pkg
    # -- Compiling entity cmd_intr
    # -- Compiling architecture bhv of cmd_intr
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity std_emulator
    # -- Compiling architecture behavioral of std_emulator
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity local_interrupter
    # -- Compiling architecture behavioral of local_interrupter
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity mc_emulator
    # -- Compiling architecture behave of mc_emulator
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity clk_gen
    # -- Compiling architecture behave of clk_gen
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_245
    # -- Compiling architecture behave of logic_245
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_a
    # -- Compiling architecture behave of logic_543_a
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_d8
    # -- Compiling architecture behave of logic_543_d8
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_d16
    # -- Compiling architecture behave of logic_543_d16
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity data_buffer
    # -- Compiling architecture behave of data_buffer
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity buffer_cntrl_analyser
    # -- Compiling architecture behave of buffer_cntrl_analyser
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity tb_top
    # -- Compiling architecture behave of tb_top
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity int_top
    # -- Compiling architecture behave of int_top
    # 0
    # Reading filenames from D:/Projects/controller/code/tb/sim/design_tc.txt
    # Running Test Case  :  tc_ctrl_01
    # vsim -coverage -t ps work.int_top
    # ** Note: (vsim-3812) Design is being optimized...
    # Loading std.standard
    # Loading ieee.std_logic_1164(body)
    # Loading ieee.std_logic_arith(body)
    # Loading ieee.std_logic_unsigned(body)
    # Loading work.int_top(behave)#1
    # Loading work.controller_top(rtl)#1
    # Loading work.controller_top1(rtl)#1
    # Loading work.sys_clk_divider(rtl)#1
    # Loading work.rst_logic(rtl)#1
    # Loading work.fair_time_out(rtl)#1
    # Loading work.std_bus_arbiter(rtl)#1
    # Loading work.bbsy_gen(rtl)#1
    # Loading work.trans_timeout_timer(rtl)#1
    # Loading work.std_bus_releaser(rtl)#1
    # Loading work.add_mod_encoder(rtl)#1
    # Loading work.std_bus_requester(rtl)#1
    # Loading work.buffer_cntr(rtl)#1
    # Loading work.ctrl_reg1(rtl)#1
    # Loading work.con_sig_trans(rtl)#1
    # Loading work.controller_top2(rtl)#1
    # Loading work.interrupt_controller(rtl)#1
    # Loading work.ctrl_reg2(rtl)#1
    # Loading work.tb_top(behave)#1
    # Loading work.clk_gen(behave)#1
    # Loading std.textio(body)
    # Loading std_developerskit.std_iopak(body)
    # Loading ieee.std_logic_textio(body)
    # Loading work.io_utils(body)
    # Loading work.std_tb_pkg(body)
    # Loading work.cmd_intr(bhv)#1
    # Loading work.mc_emulator(behave)#1
    # Loading work.std_emulator(behavioral)#1
    # Loading work.buffer_cntrl_analyser(behave)#1
    # Loading work.local_interrupter(behavioral)#1
    # Loading work.logic_543_a(behave)#1
    # Loading work.data_buffer(behave)#1
    # Loading work.logic_245(behave)#1
    # Loading work.logic_543_d16(behave)#1
    # Loading work.logic_543_d8(behave)#1
    # ** Error: (vsim-3855) HREAD Error: Read a ' z ', expected a Hex character (0-F).
    #    Time: 40240 ns  Iteration: 1  Process: /int_top/tb_top_i/cmd_intr_i/interpretation File: D:/projects/controller/code/tb/src/cmd_intr.vhd
    # Break in Process interpretation at D:/projects/controller/code/tb/src/cmd_intr.vhd line 268
    # Simulation Breakpoint: Break in Process interpretation at D:/projects/controller/code/tb/src/cmd_intr.vhd line 268
    # MACRO D:\projects\controller\code\tb\sim\design_run.do PAUSED at line 299


    I guess that there is some compatibility setting which needs to be done?
    How can I successfully simulate the design in Questasim 6.4c?
    Please help.
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    dave_59
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    PostPosted: Fri Feb 24, 2012 11:39 am    Post subject: Reply with quote

    http://www.mentor.com/supportnet/member/technotes/public/solution/mg61293.html

    The HREAD() procedure is being used to read up to 8 hex characters per line out of a file. In ModelSim 6.0x versions, this procedure allowed reading lines with 8 or 6 or 4 or 2 characters. The newer ModelSim 6.1x versions does not allow this reading of less characters than what is needed to fill up the output vector while using the same HREAD() procedure.
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    raghava216
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    PostPosted: Fri Feb 24, 2012 1:01 pm    Post subject: Reply with quote

    @Dave

    Thank you. Smile

    I could understand your post.

    HREAD() is a function in textio package of VHDL. Modelsim 6.0 and its later versions from 6.1 interpret it differently.

    But, is there a way to run it successfully on questasim 6.4c? I have to do so to complete my project.

    Pl. help.
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    dave_59
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    PostPosted: Fri Feb 24, 2012 1:19 pm    Post subject: Reply with quote

    You will either have to change the format of the file you are trying to read, or write your own procedure to read the file. I don't know much about the HREAD procedure.
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    apfitch
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    PostPosted: Sat Feb 25, 2012 6:22 am    Post subject: Reply with quote

    Hi,
    as Dave says, behaviour has changed in those versions.

    I'd like to add a couple of points.

    1. If you are using VHDL 2002 and earlier (which seems likely with an older version of Questasim), HREAD is *not* part of the VHDL standard. It was in a proprietary package STD_LOGIC_TEXTIO which was written by Synopsys, but made freely available. It is *not* part of TEXTIO.


    2. As far as I understand, the implementation of HREAD in Modelsim 6.0 is wrong. 6.4c is correct.

    3. Therefore I agree with Dave - either change the format of the file, or write your own HREAD procedure. For instance you could write an HREAD procedure that substitutes characters that are e.g. 'Z' with '0'.

    regards
    Alan
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    raghava216
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    PostPosted: Sat Feb 25, 2012 8:47 am    Post subject: Reply with quote

    @Alan

    I do not want to change the format of the file.

    Therefore, I am looking at writing a HREAD procedure that substitutes 'Z' with '0'.. I think that will solve the problem.

    My doubts are:

    1. How do I know which version of HREAD() is being used in Questasim 6.4c?

    2. How do I write a new HREAD() procedure and make my test bench use that ? I mean Where can I locate the STD_LOGIC_TEXTIO package that is being used by Questasim? If I find that package and replace it, with modifications to HREAD and HWRITE...will the testbench run successfully?
    At the link below,
    http://www.eda.org/vhdl-std-logic/proposals/CP-007-textio.txt
    It is given that
    Quote:

    4. The original package body code includes hread and oread
    procedures for bit vectors. In the case of hread, the bit
    vector versions are not used and are not visible outside
    the package. In the case of oread, the standard-logic
    versions are based on use of the bit-vector versions,
    precluding reading of Z and X values. It appears that the
    code may have evolved over time, leading to this
    inconsistency. The code below removes the bit-vector
    versions and makes the standard-logic vector versions
    consistent with one another.

    5. [i]The hread and oread procedures in the original code do not
    correctly deal with input strings that are empty or all
    white space. This is corrected in the code below.[/b]

    So , I think I can use it and try. But, I do not know how to use in place of the package that Questasim takes by default?

    3. The 'HREAD' error comes only when I run the test case 1. Here, it reads 'Z' values from a register. That is the reason I can correlate that there is some problem in Questa HREAD in reading a 'Z'.

    But for other test cases, the 'HREAD' error is not being displayed. Instead, this is how it looks:
    Code:
    # -----  COMPILING  RTL and TB  MODULES FOR FUNCTIONAL SIMULATION ------
    # D:/Projects/controller
    # reading modelsim.ini
    # Modifying modelsim.ini
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity add_mod_encoder
    # -- Compiling architecture rtl of add_mod_encoder
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity trans_timeout_timer
    # -- Compiling architecture rtl of trans_timeout_timer
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity bbsy_gen
    # -- Compiling architecture rtl of bbsy_gen
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity buffer_cntr
    # -- Compiling architecture rtl of buffer_cntr
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity fair_time_out
    # -- Compiling architecture rtl of fair_time_out
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity con_sig_trans
    # -- Compiling architecture rtl of con_sig_trans
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity sys_clk_divider
    # -- Compiling architecture rtl of sys_clk_divider
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity ctrl_reg1
    # -- Compiling architecture rtl of ctrl_reg1
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity ctrl_reg2
    # -- Compiling architecture rtl of ctrl_reg2
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity vme_bus_arbiter
    # -- Compiling architecture rtl of vme_bus_arbiter
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity vme_bus_releaser
    # -- Compiling architecture rtl of vme_bus_releaser
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity vme_bus_requester
    # -- Compiling architecture rtl of vme_bus_requester
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity interrupt_controller
    # -- Compiling architecture rtl of interrupt_controller
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity rst_logic
    # -- Compiling architecture rtl of rst_logic
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top1
    # -- Compiling architecture rtl of controller_top1
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top2
    # -- Compiling architecture rtl of controller_top2
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity controller_top
    # -- Compiling architecture rtl of controller_top
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package textio
    # -- Compiling package io_utils
    # -- Compiling package body io_utils
    # -- Loading package io_utils
    # -- Compiling entity test
    # -- Loading package io_utils
    # -- Compiling architecture hex_test of test
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package std_iopak
    # -- Loading package io_utils
    # -- Compiling package vme_tb_pkg
    # -- Compiling package body vme_tb_pkg
    # -- Loading package vme_tb_pkg
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package textio
    # -- Loading package std_iopak
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Loading package vme_tb_pkg
    # -- Compiling entity cmd_intr
    # -- Compiling architecture bhv of cmd_intr
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity vme_emulator
    # -- Compiling architecture behavioral of vme_emulator
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity local_interrupter
    # -- Compiling architecture behavioral of local_interrupter
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity mc_emulator
    # -- Compiling architecture behave of mc_emulator
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity clk_gen
    # -- Compiling architecture behave of clk_gen
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_245
    # -- Compiling architecture behave of logic_245
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_a
    # -- Compiling architecture behave of logic_543_a
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_d8
    # -- Compiling architecture behave of logic_543_d8
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity logic_543_d16
    # -- Compiling architecture behave of logic_543_d16
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity data_buffer
    # -- Compiling architecture behave of data_buffer
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Loading package textio
    # -- Loading package std_logic_textio
    # -- Loading package io_utils
    # -- Compiling entity buffer_cntrl_analyser
    # -- Compiling architecture behave of buffer_cntrl_analyser
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity tb_top
    # -- Compiling architecture behave of tb_top
    # QuestaSim vcom 6.4c Compiler 2008.12 Dec  8 2008
    # -- Loading package standard
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_arith
    # -- Loading package std_logic_unsigned
    # -- Compiling entity int_top
    # -- Compiling architecture behave of int_top
    # 0
    # Reading filenames from D:/Projects/controller/code/tb/sim/design_tc.txt
    # Running Test Case  :  tc_ctrl_11
    # vsim -coverage -t ps work.int_top
    # ** Note: (vsim-3812) Design is being optimized...
    # Loading std.standard
    # Loading ieee.std_logic_1164(body)
    # Loading ieee.std_logic_arith(body)
    # Loading ieee.std_logic_unsigned(body)
    # Loading work.int_top(behave)#1
    # Loading work.controller_top(rtl)#1
    # Loading work.controller_top1(rtl)#1
    # Loading work.sys_clk_divider(rtl)#1
    # Loading work.rst_logic(rtl)#1
    # Loading work.fair_time_out(rtl)#1
    # Loading work.vme_bus_arbiter(rtl)#1
    # Loading work.bbsy_gen(rtl)#1
    # Loading work.trans_timeout_timer(rtl)#1
    # Loading work.vme_bus_releaser(rtl)#1
    # Loading work.add_mod_encoder(rtl)#1
    # Loading work.vme_bus_requester(rtl)#1
    # Loading work.buffer_cntr(rtl)#1
    # Loading work.ctrl_reg1(rtl)#1
    # Loading work.con_sig_trans(rtl)#1
    # Loading work.controller_top2(rtl)#1
    # Loading work.interrupt_controller(rtl)#1
    # Loading work.ctrl_reg2(rtl)#1
    # Loading work.tb_top(behave)#1
    # Loading work.clk_gen(behave)#1
    # Loading std.textio(body)
    # Loading std_developerskit.std_iopak(body)
    # Loading ieee.std_logic_textio(body)
    # Loading work.io_utils(body)
    # Loading work.vme_tb_pkg(body)
    # Loading work.cmd_intr(bhv)#1
    # Loading work.mc_emulator(behave)#1
    # Loading work.vme_emulator(behavioral)#1
    # Loading work.buffer_cntrl_analyser(behave)#1
    # Loading work.local_interrupter(behavioral)#1
    # Loading work.logic_543_a(behave)#1
    # Loading work.data_buffer(behave)#1
    # Loading work.logic_245(behave)#1
    # Loading work.logic_543_d16(behave)#1
    # Loading work.logic_543_d8(behave)#1
    # ** Failure: Simulation Finished
    #    Time: 25440 ns  Iteration: 1  Process: /int_top/tb_top_i/mc_emulator_i/report_gen File:

    D:/projects/controller/code/tb/src/mc_emulator.vhd
    # Break in Process report_gen at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # Simulation Breakpoint: Break in Process report_gen at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # MACRO D:\projects\controller\code\tb\sim\design_run.do PAUSED at line 299




    I am reading a lot. But, confused and not getting an idea how to proceed towards solution.
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    Ajeetha
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    Joined: Mar 29, 2004
    Posts: 425
    Location: Bengaluru, India

    PostPosted: Sun Feb 26, 2012 3:40 am    Post subject: Reply with quote

    Hi,

    raghava216 wrote:
    @Alan

    I do not want to change the format of the file.

    Therefore, I am looking at writing a HREAD procedure that substitutes 'Z' with '0'.. I think that will solve the problem.

    My doubts are:

    1. How do I know which version of HREAD() is being used in Questasim 6.4c?



    Typically $QUESTA_HOME/vhdl_src can give you clues. As Alan mentioned since std_logic_textio was not part of IEEE, Questa usually has it under vhdl_src/synopsys/std_logic_textio.vhd

    Do some look around that and find your matching HREAD.

    Quote:

    2. How do I write a new HREAD() procedure and make my test bench use that ? I mean Where can I locate the STD_LOGIC_TEXTIO package that is being used by Questasim? If I find that package and replace it, with modifications to HREAD and HWRITE...will the testbench run successfully?


    If you clearly can identify the format of text file and the requirement for your HREAD this is doable. Assuming you can modify your testbench/testcase, you can even compile this new package/hread and ask vhdl to use it (Power of library/package - namespace as in OOP world).

    Quote:

    # Loading work.logic_543_d8(behave)#1
    # ** Failure: Simulation Finished
    # Time: 25440 ns Iteration: 1 Process: /int_top/tb_top_i/mc_emulator_i/report_gen File:


    Presumably you use old styled "assert false report .. failure" trick to end test. VHDL-2008 has enhanced with std.env.stop/finish to do better. We cover it in our advanced VHDL training sessions involving modern verification approaches including Assertions, coverage etc. Contact us via training@cvcblr.com or www.cvcblr.com if interested in details.

    Also you may want to look at recent VHDL Verif Methodology at:

    http://www.electronics-eetimes.com/en/open-source-vhdl-verification-methodology-extended.html?cmp_id=7&news_id=222910734#

    Quote:

    I am reading a lot. But, confused and not getting an idea how to proceed towards solution.


    It is indeed fun to do in VHDL, let us know if you still need assistance.

    Regards
    Ajeetha, CVC
    www.cvcblr.com/blog
    _________________
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    CVC Pvt Ltd. http://www.cvcblr.com
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    raghava216
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    PostPosted: Mon Feb 27, 2012 4:15 am    Post subject: Reply with quote

    Ajeetha wrote:
    Hi,

    raghava216 wrote:
    @Alan

    I do not want to change the format of the file.

    Therefore, I am looking at writing a HREAD procedure that substitutes 'Z' with '0'.. I think that will solve the problem.

    My doubts are:

    1. How do I know which version of HREAD() is being used in Questasim 6.4c?



    Typically $QUESTA_HOME/vhdl_src can give you clues. As Alan mentioned since std_logic_textio was not part of IEEE, Questa usually has it under vhdl_src/synopsys/std_logic_textio.vhd

    Do some look around that and find your matching HREAD.

    Quote:

    2. How do I write a new HREAD() procedure and make my test bench use that ? I mean Where can I locate the STD_LOGIC_TEXTIO package that is being used by Questasim? If I find that package and replace it, with modifications to HREAD and HWRITE...will the testbench run successfully?


    If you clearly can identify the format of text file and the requirement for your HREAD this is doable. Assuming you can modify your testbench/testcase, you can even compile this new package/hread and ask vhdl to use it (Power of library/package - namespace as in OOP world).

    Quote:

    # Loading work.logic_543_d8(behave)#1
    # ** Failure: Simulation Finished
    # Time: 25440 ns Iteration: 1 Process: /int_top/tb_top_i/mc_emulator_i/report_gen File:


    Presumably you use old styled "assert false report .. failure" trick to end test. VHDL-2008 has enhanced with std.env.stop/finish to do better. We cover it in our advanced VHDL training sessions involving modern verification approaches including Assertions, coverage etc. Contact us via training@cvcblr.com or www.cvcblr.com if interested in details.

    Also you may want to look at recent VHDL Verif Methodology at:

    http://www.electronics-eetimes.com/en/open-source-vhdl-verification-methodology-extended.html?cmp_id=7&news_id=222910734#

    Quote:

    I am reading a lot. But, confused and not getting an idea how to proceed towards solution.


    It is indeed fun to do in VHDL, let us know if you still need assistance.

    Regards
    Ajeetha, CVC
    www.cvcblr.com/blog


    @Ajeetha

    Thank you for providing me very useful information.

    I could locate 'STD_LOGIC_TEXTIO.VHD' in the Questa installation directory.

    Now, I compared this one with the 'STD_LOGIC_TEXTIO.VHD' as in the Modelsim 6.0 SE installation directory.

    Both are exactly the same. I am not able to identify what is causing the simulation to break in questa?

    Also, When the simulation is run in modelsim 6.0 SE for the first time ( irrespective of whether the previously created 'work' directory is deleted or not) It throws an error and simulation breaks with the message and reports are not getting generated.

    Quote:
    # ** Failure: Simulation Finished
    # Time: 51480 ns Iteration: 1 Process: /int_top/tb_top_i/mc_emulator_i/report_gen File: D:/projects/controller/code/tb/src/mc_emulator.vhd
    # Break at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # Simulation Breakpoint: Break at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # MACRO D:\projects\controller\code\tb\sim\design.do PAUSED at line 299


    Now, from second time onwards i.e. if I repeat the simulation in modelsim 6.0 SE by executing the macro again (irrespective of whether the previously created 'work' directory is deleted or not), It throws the following message. Reports are generated and no errors in the simulation process.

    Quote:
    # ** Failure: Simulation Finished
    # Time: 51480 ns Iteration: 1 Process: /int_top/tb_top_i/mc_emulator_i/report_gen File: D:/projects/controller/code/tb/src/mc_emulator.vhd
    # Break at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # tc_ctrl_01 Test Case Completed at Time : 51480000 ns


    I am not able to trace the cause for this kind of behavior.

    And in Questasim,

    when I run the test case 1, wherein a 'Z' value is read from a register, it gives a HREAD error and the displayed message as posted by me in my first post in the thread is as follows:
    Quote:

    # ** Error: (vsim-3855) HREAD Error: Read a ' z ', expected a Hex character (0-F).
    # Time: 40240 ns Iteration: 1 Process: /int_top/tb_top_i/cmd_intr_i/interpretation File: D:/projects/controller/code/tb/src/cmd_intr.vhd
    # Break in Process interpretation at D:/projects/controller/code/tb/src/cmd_intr.vhd line 268
    # Simulation Breakpoint: Break in Process interpretation at D:/projects/controller/code/tb/src/cmd_intr.vhd line 268
    # MACRO D:\projects\controller\code\tb\sim\design_run.do PAUSED at line 299


    When the simulation is run from second time onwards, the behavior is same and it is unlike that in modelsim 6.0 SE, where it was successful.

    With other test cases, which do not deal with 'Z' values, the message is as follows:
    Quote:
    # Time: 51480 ns Iteration: 1 Process: /int_top/tb_top_i/mc_emulator_i/report_gen File: D:/projects/controller/code/tb/src/mc_emulator.vhd
    # Break at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # Simulation Breakpoint: Break at D:/projects/controller/code/tb/src/mc_emulator.vhd line 787
    # MACRO D:\projects\controller\code\tb\sim\design.do PAUSED at line 299


    This is the summary of the issues I am facing.

    Looking fwd for ur reply.[/code]
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    apfitch
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    PostPosted: Mon Feb 27, 2012 7:55 am    Post subject: Reply with quote

    Hi,
    actually I've thought of an easier way. I assume that your data is fixed width, and is a multiple of 4 bits - but contains 'z's. For instance

    ZZZZBEEF

    In that case, you could re-write the line buffer after calling READLINE. E.g.

    Code:

    READLINE(F.L);
    for I in 1 to L'LENGTH loop
      if (L(I) = 'z') or (L(i) = 'Z') then
         L(I) =  '0';
      end if;
    end loop;

    HREAD(L, S);


    Obviously this assumes the line in your file only contains hex numbers with 'z' or 'Z' in them. If it's more complicated than that, my proposal won't work,

    regards Alan
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    JimLewis
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    PostPosted: Mon Feb 27, 2012 12:34 pm    Post subject: Reply with quote

    @raghava216
    If it is an upper case 'Z' you are trying to read, turn on the VHDL-2008 switch in ModelSim. You can do this on the command line in ModelSim by :
    vcom -2008

    You can also make VHDL-2008 the default through the GUI:
    Compile > Compile Options > Use 1076-2008

    In VHDL-2008, hread can read 'Z' and 'X'. It is likely that you had enabled VHDL-2008 through the GUI in the previous version of ModelSim and forgot to do it for the new version.

    If it is a lower case 'z', you will want to fix your files. If the file only contains hex characters, you should be able to make all of the characters in the file upper case.

    OTOH, if you decide to create your own procedures, be sure to name them something different than hread (or hex_read). In VHDL-2008 these procedures are in std_logic_1164. You no longer need to use std_logic_textio, but it is ok to include it since it only has aliases in it to std_logic_1164.

    Best Regards,
    Jim

    P.S.
    For constrained random and coverage driven verification with VHDL be sure to get our OS-VVM packages at: http://www.synthworks.com/downloads
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    raghava216
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    PostPosted: Tue Feb 28, 2012 12:43 am    Post subject: Reply with quote

    @Jim

    Thanks for ur reply.

    Yes. I am trying to read a uppercase 'Z'.

    But, I am running it in questasim 6.4c, which does not have vhdl 2008 support. it supports upto vhdl-2002 only.

    and in modelsim 6.0 SE, there is no problem.

    P.S : I am using old versions of modelsim and questasim because I have license only for them and at this stage I cannot afford to upgrade them.

    @Alan

    Thanks for ur reply.

    Your proposal might just work.

    The data is 8'bZ actually. It is a register data in initial state.

    I did not get where to place the code snippet that you posted here.

    I do not see 'READLINE' in STD_LOGIC_TEXTIO.VHD.
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    apfitch
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    PostPosted: Wed Feb 29, 2012 10:07 am    Post subject: Reply with quote

    Hi,
    READLINE should be in your VHDL code just before the call to HREAD.

    However I don't expect HREAD to work with 8'b0, that's a Verilog format, not a VHDL format.

    regards
    Alan
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    PostPosted: Thu Mar 01, 2012 12:08 am    Post subject: Reply with quote

    @Alan

    My bad... I should have written "ZZZZZZZZ"...

    Its the same in the program
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