| Login | | Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. | |
| Who's Online | There are currently, 35 guest(s) and 0 member(s) that are online.
You are Anonymous user. You can register for free by clicking here | |
 | |
|
Verification Guild: Forums |
|
| View previous topic :: View next topic |
| Author |
Message |
ruchi123456789 Junior


Joined: Jan 23, 2012 Posts: 6
|
Posted: Mon Jan 23, 2012 12:29 pm Post subject: System verilog assertions checks for 50% duty cycle ! |
|
|
HI all,
I am fresher in this field.
Could you please help me for System verilog assertions checks for 50% duty cycle ,
and 25/75 % duty cycle checks .
There are two clks ,For fist clk I need to check 50% duty cycle
and for other 25/75 % duty cycle .
Thanks in advance .
Ruchi |
|
| Back to top |
|
 |
vhdlcohen Industry Expert


Joined: Jan 05, 2004 Posts: 1237 Location: Los Angeles, CA
|
|
| Back to top |
|
 |
ruchi123456789 Junior


Joined: Jan 23, 2012 Posts: 6
|
Posted: Mon Feb 20, 2012 6:14 am Post subject: |
|
|
| Thanks alot |
|
| Back to top |
|
 |
|
|
You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum
|
| |
|
|