A Community of Verification Professionals

Create an Account	Home | Calendar | Downloads | FAQ | Links | Site Admin | Your Account
Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 58 guest(s) and 1 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Overriding Specparam using SDF OR PLI          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message arvi Senior Joined: Apr 18, 2007 Posts: 41 Location: Chandler, AZ Posted: Mon Jun 23, 2008 6:40 pm    Post subject: Overriding Specparam using SDF OR PLI Hi, My behavioural model has specparams defined for certain delays and timing checks. Actually these delays are huge and in 'ms'. I can only override these delays with a SDF file. A simplest form of SDF file should do it?? I'm looking at the web for help. Any of you came across stuff like this before? A link or a recommendation could help. Thank You Arvi Last edited by arvi on Thu Jun 26, 2008 12:14 pm; edited 1 time in total Back to top defineview Junior Joined: Jun 19, 2008 Posts: 6 Location: Los Gatos, Ca Posted: Tue Jun 24, 2008 12:00 am    Post subject: Re: Overriding Specparam using SDF arvi wrote: My behavioural model has specparams defined for certain delays and timing checks. Actually these delays are huge and in 'ms'. I can only override these delays with a SDF file. A simplest form of SDF file should do it?? I'm looking at the web for help. Any of you came across stuff like this before? A link or a recommendation could help. Arvi, You are correct that specparam values can only be over written with an SDF file (defparams unfortunately don't work here). Here's an example that I cooked up from some (very!) old notes. Please take it with a grain of salt. I haven't had a chance to simulate this yet.. Code: YOUR DESIGN MODULE:: module LIB_BUF (O,I); output O; input I; buf (O,I); specify    specparam LH = 0:0:0, HL = 0:0:0;    (I => O) = (LH,HL); endspecify endmodule Code: INSTANCE OF LIB_BUF:: LIB_BUF LB1(.I(bufIN), .O(bufOUT)); Code: SDF FILE (bufPL.sdf) TO ANNOTATE TO LIB_BUF:: (DELAYFILE (SDFVERSION "3.0") (DESIGN "COOLSOC") (DATE "May 1, 2000 02:46") (VENDOR "ABCD ASIC") (PROGRAM "Cool program") (VERSION "1.26") (DIVIDER /) (VOLTAGE 5.5:5.0:4.5) (PROCESS "best:nom:worst") (TEMPERATURE -40:25:125) (TIMESCALE 100 ps) (CELL   (CELLTYPE "LIB_BUF")   (INSTANCE LB1)   (DELAY     (ABSOLUTE     (IOPATH I O (2:3:4) (3:4:5))     )   ) ) Code: SDF task in your Verilog testbench: initial $sdf_annotate(“bufPL.sdf”); Hope that helps.... -Ashok http://defineview.com/ Back to top arvi Senior Joined: Apr 18, 2007 Posts: 41 Location: Chandler, AZ Posted: Tue Jun 24, 2008 11:41 am    Post subject: Ashok, Thanks. This is similar to what I was looking for. In my case though, they are rather counters instead of path delays. Like for instance a counter value is defined to be 24 ms. [Terase = 24,000,000] And it is a specparam in the behavioral model. I've not found an example that overrides the specparam constant in the original model. The model by itself is a pretty complex one and I need to override only a few specparams to speed up my simulation. I'm gonna give it a try today and see. Meantime any help is much appreciated. -Arvi Back to top defineview Junior Joined: Jun 19, 2008 Posts: 6 Location: Los Gatos, Ca Posted: Tue Jun 24, 2008 12:41 pm    Post subject: arvi wrote: ... I've not found an example that overrides the specparam constant in the original model. The model by itself is a pretty complex one and I need to override only a few specparams to speed up my simulation. -Arvi Arvi, As far as I know, a specparam constant can not be over written directly. In other words, a specparam is used in path delays, timing checks, etc. (only in the specify block) and it's the delays of these paths/timing checks that can be overwritten by back-annotation with a SDF. I don't think there's a way to directly overwrite the specparam value itself. Also, in case you don't have the latest SDF document, here's the link. I haven't had a chance to go through it in detail but if you find something contrary to what I've said, please do share. http://www.eda.org/sdf/sdf_3.0.pdf Regards. -Ashok _________________ DefineView Consulting :: http://defineview.com/ Advanced Training/Consulting in * System Verilog Assertions * Functional Coverage * Constrained Random Verification Back to top arvi Senior Joined: Apr 18, 2007 Posts: 41 Location: Chandler, AZ Posted: Tue Jun 24, 2008 1:28 pm    Post subject: Thanks again, Ashok. I'll try it to come up with a crude sdf with constant values and see what happens. Thanks -Arvi Back to top arvi Senior Joined: Apr 18, 2007 Posts: 41 Location: Chandler, AZ Posted: Thu Jun 26, 2008 12:14 pm    Post subject: Hi, From what I learnt in the last couple of days, SDF can not be used overwrite the contstant itself. There was a mentioning that PLI can be used to re-define specparams. I tried that route also, and to my surprise PLI allows you only to read the specparam constants not writing. WOW!! -Arvi Back to top balasub Senior Joined: Dec 16, 2007 Posts: 48 Posted: Mon Jun 30, 2008 7:05 am    Post subject: hi arvi, i am also facing a similar problem like yours in my gate-level simulation. I have some delays which are quite large but these are shortened in normal RTL simulation ofcourse. Hence i am having a tough time figuring out to run my netlist simulation.. Please share ur experience... Some parameters are in ms like u mentioned since this netlist is generated after sythesis and is close to the real hardware settings. Thanks! Back to top TomDigHead Newbie Joined: Dec 30, 2011 Posts: 1 Posted: Fri Dec 30, 2011 11:05 am    Post subject: Thanks Ashok your solution to use sdf_annotate worked well! I was getting bogus a bogus timing check error so I needed to increase the default gate delay of the BUF driving the D input to the D-FF and your solution allow me to increase the delay from 1ns to 2ns no more X's causing the sim to fail. - TomDigHead Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

Verification Guild © 2006 Janick Bergeron
Web site engine's code is Copyright © 2003 by PHP-Nuke. All Rights Reserved. PHP-Nuke is Free Software released under the GNU/GPL license.
Page Generation: 0.242 Seconds