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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 62 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  vhdl: drawbacks of having unused library and use clauses          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message ljepson Senior Joined: Jan 29, 2006 Posts: 24 Location: Mtn. View, CA Posted: Fri Dec 09, 2011 6:23 pm    Post subject: vhdl: drawbacks of having unused library and use clauses Is there a problem (such as longer compile times) with having the 'library' and 'use' clauses as a template block at the top of each vhdl file? Perhaps we just bundle it with the company header and use it as boilerplate across the entire design. i.e. if one module needs a new function, its library/use clause is added to the template which is put into all files. Objective: Keep all team on same page of what packages/functions are available. Save time of having to hunt around to discover which library/package holds a function that you want to use (that someone else is using elsewhere in a design). -- ----------------------------------------------------------------------------- -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. linc jepson -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. lorem ipsum -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.or_reduce; -- use homemade packages below library work; use work.hard_pack.all; use work.soft_pack.all; Back to top Ajeetha Senior Joined: Mar 29, 2004 Posts: 424 Location: Bengaluru, India Posted: Sat Dec 10, 2011 3:16 pm    Post subject: Re: vhdl: drawbacks of having unused library and use cla Hello, ljepson wrote: Is there a problem (such as longer compile times) with having the 'library' and 'use' clauses as a template block at the top of each vhdl file? Perhaps we just bundle it with the company header and use it as boilerplate across the entire design. Not in general, some tools do a "refresh" of libraries during "incremental compile" (aka smartordering etc.). That may impact. Quote: i.e. if one module needs a new function, its library/use clause is added to the template which is put into all files. Objective: Keep all team on same page of what packages/functions are available. Save time of having to hunt around to discover which library/package holds a function that you want to use (that someone else is using elsewhere in a design). -- ----------------------------------------------------------------------------- -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. linc jepson -- Some company header here. Some company header here. lorem ipsum -- Some company header here. Some company header here. lorem ipsum -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.or_reduce; -- use homemade packages below library work; use work.hard_pack.all; use work.soft_pack.all; BTW - new VHDL 2008 introduced "context" precisely for such usage. In your example you could do: Code: context ipsum_proj is   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.or_reduce; -- use homemade packages below library work; use work.hard_pack.all; use work.soft_pack.all; end context ipsum_proj; And in all your project files, simply use: Code:   context ipsum_proj;  -- remaining code Check if your EDA tool supports it already, if not, ask for it! Regards Ajeetha, CVC www.cvcblr.com/blog _________________ Ajeetha Kumari, CVC Pvt Ltd. http://www.cvcblr.com * A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/ * SystemVerilog Assertions Handbook * Using PSL/Sugar Back to top ljepson Senior Joined: Jan 29, 2006 Posts: 24 Location: Mtn. View, CA Posted: Tue Dec 13, 2011 3:53 pm    Post subject: Thank you very much, Ajeetha. Linc Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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