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Bren
Junior
Joined: Aug 02, 2004
Posts: 5
Location: UK
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 Posted: Mon Sep 20, 2004 8:44 am Post subject: Resetting TB state |
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Hi.
I'm developing a Verilog TB with several tasks, some of which schedule events in future sim-time.
If for some reason I want to reset the sim state, (say on detection of a deadlock condition), is there a way I can 'de-schedule' those future events, or so I have to start again?
Thanks. |
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alexg
Senior
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Joined: Jan 07, 2004
Posts: 586
Location: Ottawa
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| Posted: Mon Sep 20, 2004 11:29 pm Post subject: |
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Generally speaking, you cannot 'de-schedule' the task. In order to achieve this, you have to re-write your tasks to support this feature. In the following example, task "incr_i" exits immediately once deadlock is asserted. Otherwise, it will continue normal execution.
| Code: | module test;
integer i; initial i = 0;
reg clk; initial clk = 0;
reg deadlock; initial deadlock = 0;
always #10 clk <= ~clk;
/* (example of original task)
task incr_i;
begin
$display("@%0t: invoking incr_i task", $time);
#40 i = 1;
#40 i = 2;
#40 i = 3;
#40 i = 4;
end
endtask
*/
task incr_i;
begin
$display("@%0t: invoking incr_i task", $time);
if (!deadlock) #40 i = 1;
if (!deadlock) #40 i = 2;
if (!deadlock) #40 i = 3;
if (!deadlock) #40 i = 4;
if (deadlock) i = 0; //initial value
end
endtask
initial incr_i;
always @(negedge deadlock) incr_i;
initial begin
$monitor("@%0t: i=%0d, deadlock = %b",$time, i, deadlock);
#100 deadlock = 1;
#1 deadlock = 0;
#1000 $finish;
end
endmodule
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Regards,
Alexander Gnusin |
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Bren
Junior
Joined: Aug 02, 2004
Posts: 5
Location: UK
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| Posted: Tue Sep 21, 2004 3:35 am Post subject: |
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Thanks for that.
That would prevent a task from making further assinments, but is there also some way to de-schedule future events that have already been scheduled?
For example, if a task had made the assignment:
#2000 clk_en = 1'b1;
...but I wanted to re-start my simulation only 100 time-steps after this assignment, then the event would still be scheduled.
- Bren |
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Ajeetha
Senior
Joined: Mar 29, 2004
Posts: 424
Location: Bengaluru, India
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| Posted: Tue Sep 21, 2004 6:38 am Post subject: |
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| Bren wrote: | Thanks for that.
That would prevent a task from making further assinments, but is there also some way to de-schedule future events that have already been scheduled?
For example, if a task had made the assignment:
#2000 clk_en = 1'b1;
...but I wanted to re-start my simulation only 100 time-steps after this assignment, then the event would still be scheduled.
- Bren |
Hi,
In Verilog, there is a way to disable a named block (look for "disable" construct), be it a task or a for loop etc. But I am not sure how you can "enable" it back without doing "restart" in your simulator - have you already figured that out?
Ajeetha
http://www.noveldv.com
_________________
Ajeetha Kumari,
CVC Pvt Ltd. http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar |
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