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Narek
Newbie
Joined: Aug 31, 2004
Posts: 1
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 Posted: Tue Aug 31, 2004 3:14 am Post subject: Hierarchial Signal Names in PSL/OVL |
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Hi,
I am currently assessing and testing the possible use of PSL or OVL within our organisation. I am trying to find out if it's possible to use signals across the hierarchy within assertions. So far my searches on the matter haven't been confirmed nor denied. Any information would be helpful.
Thanks,
Narek |
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vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1248
Location: Los Angeles, CA
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| Posted: Wed Sep 08, 2004 12:06 pm Post subject: |
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| Quote: | | I am currently assessing and testing the possible use of PSL or OVL within our organisation. I am trying to find out if it's possible to use signals across the hierarchy within assertions. So far my searches on the matter haven't been confirmed nor denied. Any information would be helpful. |
PSL is a language that is used in conjunction with other HDL like VHDl, Verilog , or SystemVerilog. Thus, the access of signals across the hiererchy is not a PSL issue, but rather an HDL issue. Obviously, Verilog and SystemVerilog allow you to access signals across the hierarchy. VHDL'95 is more restictive, but Mentor and Cadence provide routines to access signals across hierarchy. It's not as easy as Verilog or SystemVerilog.
OVL consists of modules or components, which are instantiated. Thus, it becaomes a matter of what is being passed to the ports.
Ben
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
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Ajeetha
Senior
Joined: Mar 29, 2004
Posts: 424
Location: Bengaluru, India
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| Posted: Wed Sep 08, 2004 1:46 pm Post subject: |
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| vhdlcohen wrote: | | VHDL'95 is more restictive, but Mentor and Cadence provide routines to access signals across hierarchy. Ben |
For the information/completeness sake, VCS & Aldec also has similar packages. One could use more generic probe package that I wrote a while ago for this, please see downloads section in this site - that kind of makes your code "virtually" simulator independent - though you need to compile different package files for different simulators, the TB code and call to the probing commands will remain unchanged.
Thanks,
Ajeetha
_________________
Ajeetha Kumari,
CVC Pvt Ltd. http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar |
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