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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 58 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Open source SystemVerilog?          Verification Guild Forum Index -> Simulation View previous topic :: View next topic   Author Message Martin1234 Senior Joined: Jan 27, 2004 Posts: 110 Posted: Sat Aug 28, 2004 3:18 pm    Post subject: Open source SystemVerilog? Is there anything (i.e. legal) that would get someone in trouble from writing an open source SystemVerilog compiler and simulator? Is the SystemVerilog language standard a proprietary language? Is there sponsored SystemVerilog project on the go somewhere? Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1237 Location: Los Angeles, CA Posted: Sat Aug 28, 2004 4:44 pm    Post subject: Quote: Is there anything (i.e. legal) that would get someone in trouble from writing an open source SystemVerilog compiler and simulator? Is the SystemVerilog language standard a proprietary language? Is there sponsored SystemVerilog project on the go somewhere? Accellera and Synopsys would love you to contribute to SystemVerilog. "Synopsys' SystemVerilog Catalyst program promotes the development and use of EDA tools, verification IP and training services supporting the SystemVerilog standard for design and verification. http://www.synopsys.com/partners/systemverilog/systemverilog_program.html Also see list of partners: http://www.synopsys.com/partners/systemverilog/systemverilog_partners.html Ben _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top Martin1234 Senior Joined: Jan 27, 2004 Posts: 110 Posted: Sat Aug 28, 2004 5:01 pm    Post subject: That does not answer the question. Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1237 Location: Los Angeles, CA Posted: Sat Aug 28, 2004 5:08 pm    Post subject: I am not a lawyer, but my undestanding is that SystemVerilog is an "open" language, like Verilog or VHDL, but unlike SPecman. Thus, it should be legal to write a compiler and simulator that meets the requirements of SystemVerilog. You can even write books about the subject! Ben Cohen _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top Martin1234 Senior Joined: Jan 27, 2004 Posts: 110 Posted: Sat Aug 28, 2004 6:45 pm    Post subject: Thanks vhdlcohen! I looked it up on the systemverilog.org web page and there is no apparent legal restriction on the language. Somehow I thought that SV was a proprietary language. Back to top elavelle Junior Joined: Jun 15, 2004 Posts: 9 Posted: Sun Aug 29, 2004 11:20 am    Post subject: The current LRM is copyrighted by Accellera so I think that, technically, they could do what they want, including stopping you from delivering a compatible product. This will change if/when the copyright is transferred to the IEEE. If you're talking about open-source projects, then I suspect that SV is so complex that this'll never happen. It'll certainly take a few years. Evan Back to top Martin1234 Senior Joined: Jan 27, 2004 Posts: 110 Posted: Sun Aug 29, 2004 12:55 pm    Post subject: Quote: The current LRM is copyrighted by Accellera so I think that, technically, they could do what they want, including stopping you from delivering a compatible product. This will change if/when the copyright is transferred to the IEEE. I guess there are three aspects to the question: 1) Is SystemVerilog a free programming language, i.e. can someone develop tools (compiler, simulator, etc.) that are free of limitations and restrictions providing those tools do not infringe on existing patents? 2) Would the developer have to pay royalties to develop tools for the SystemVerilog programming language? and 3), can those tools be open source and provided under a free license such as GPL? I read the statement of use in the SystemVerilog LRM, and nothing seems to limit someone from implementing a GPL version of compilers, simulators or other tools for the language, but somehow I suspect some language constructs are patented (patents for a specialized language statement). Back to top dave_59 Senior Joined: Jun 22, 2004 Posts: 974 Location: Fremont, CA Posted: Mon Aug 30, 2004 1:03 am    Post subject: SystemVerilog coptyright and patents You may want to look at: http://standards.ieee.org/faqs/copyrightFAQ.html and http://standards.ieee.org/guides/bylaws/sect6-7.html#6 Basically, the text of the LRM is copyrighted and can only be reprinted or redistributed by permission, but the standard itself is based on work free of patents or licensing. This was a requirement for the donation to Accellera, and then to the IEEE. So start coding. Back to top Darren Senior Joined: Jan 06, 2004 Posts: 32 Location: Bristol, England Posted: Tue Aug 31, 2004 3:53 am    Post subject: vhdlcohen wrote: I am not a lawyer, but my undestanding is that SystemVerilog is an "open" language, like Verilog or VHDL, but unlike SPecman. Thus, it should be legal to write a compiler and simulator that meets the requirements of SystemVerilog. You can even write books about the subject! Ben Cohen The Specman tool itself may not be open, but the e language is as it is going through the IEEE standardisation process - you can go to http://www.ieee1647.org/downloads.html and download the LRM and an open source parser. Saying that Specman is not open is like saying VCS or Affirma-NC are not open, when the HDL languages that they simulate are. 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