Verification Education

bunker · Posted: Tue Aug 24, 2004 10:15 am **Post subject: Verification Education**

I'm an ECE professor at Utah State University in Logan, Utah, USA. We are building a verification program, and as a part of that, are designing a course on functional verification. We'll probably model it somewhat after the course taught by The Ohio State University and now others (http://www.cse.psu.edu/~vijay/verify/instructors.html), which is heavily project oriented.

I generally teach methods and philosophies independent of tools, using a particular tool suite to illustrate one implementation of the methods and philosophies. I'm aware of the following possible texts, but wonder if you all know of any others at which I should look.

1. Janick's Writing Testbenches, Kluwer
2. Bening and Foster, Principles of Verifiable RTL Design, Kluwer
3. James, Verification Plans, Kluwer
4. Palnitkar, Design Verification with e, Prentice Hall
5. I thought I saw an ad for one coming from John Wiley and Sons, but my website searches are turning up empty. Was I hallucinating?

Also, if you had 15 weeks with 20 senior undergraduate and lower division graduate ECE students, what are the top 3-5 verification topics/ideas you would try to instill in them?

Thanks tons,
Annette

Larry · Senior Joined: May 24, 2004 Posts: 10

Try to break the design, rather than simply show it working.

The functional verification environment and tests must be reproducible.

Don’t underestimate the value of simply proofreading design code.

Even with a passing test case on every requirement, bugs can still lurk.

There should be no unused compute time in a verification effort.

vhdlcohen · Posted: Tue Aug 24, 2004 12:24 pm **Post subject:**

You should also include the subject of "Assertion-Based Verification", and its impact in the definition of requirements, testplan, and verification thru dynamic (simulation) and static (formal) means. The book Assertion-Based Design, Second Edition
Harry D. Foster, Adam C. Krolnik, David J. Lacey is very good.

I co-authored the book "Using PSL for formal and Dynamic Verification, 2nd edition, and we're working on a follow-up book due in Ocotober on "Using System Verilog Assertions for Formal and Dynamic Verification". Those books address, with lots of examples, the practical use of ABV languages in the design and verification process (see my site for more info).

Speaking of books, I also have " Real Chip Design and Verification Using Verilog and VHDL" that addresses traditional verification techniques by example (no ABV techniques). That might also be of interest to you.
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books

Janick · Posted: Tue Aug 24, 2004 4:15 pm **Post subject: Re: verification education**

srini · Posted: Wed Aug 25, 2004 12:31 pm **Post subject: Re: Verification Education**

jra · Junior Joined: Aug 27, 2004 Posts: 5

You may also want to look at a new book on hw/sw co-verification that includes a lot of verification information related to ARM SoC designs.

Most verification projects must also take into account embedded software.

http://coverification.home.comcast.net

Jason

bunker

Thank you, all. I knew I could count on the Guild for some concise and thought-provoking comments.

We are probably a year out from actually offering the course. I expect that I'll have more such questions for you as development progresses. I want this course to be realistic and useful to the students as they head out to your teams--well, at least as much so as I can make a class.

We are seeking public grants to help us fund development and assessment validation. Since almost all funding agencies require some sort of wide dissemination, we'll definitely let you know how it goes, one way or another.

Thanks again, for the interest, encouragement, and insights.

Annette

Darren · Posted: Tue Aug 31, 2004 3:59 am **Post subject:**

The University of Bristol in the UK also offer a course in verification as part of a degree - you might want to contact Dr Kerstin Eder to discuss things. It is a shorter course than what you are planning, but covers things such as assertions, coverage, random testing, formal methods etc. They also get people from outside to come in and give a practical talk on what is done in the "real world" - I've been invited along before to give a talk, for example.

bugfinder · Senior Joined: Jan 12, 2004 Posts: 19

Assertions are becoming more common and in many practical cases it is the verification engineer who finally puts down assertions atleast at the block interfaces. Surely it takes a different mind set and view point to write them after analysing the specifications or design document or the interface standards. Please include one assertion language(PSL or SVA) in detail as part of the curriculum.

All the best on this initiative.

Regards.