Reusing C tests and Verilog tests in Vera

VeraNewbie · Newbie Joined: Jul 26, 2004 Posts: 1

Hi,
I have a Verilog BFM and C BFM which I want to reuse in
my new Vera Environment . I also want to reuse the existing
tests in Verilog and C in Vera. What is the best way to go about it.

Thanks,
VeraNewbie

verif_eng · Newbie Joined: Jul 27, 2004 Posts: 1

Dear VeraNewbie,

It is possible to reuse your existing Verilog BFM and C BFM code in
Vera. Vera is able to call both Verilog tasks and C functions.
For example, for Vera to call an existing Verilog task found
in a BFM, do this:

hdl_task write(bit [3:0] val) "design_test_top.dut.write_bus";
program test {
write(2);
}

For Vera to call an existing C function found in a BFM, do this:

extern "C" function integer write(bit [3:0] val);
program test {
write(2);
}

Via the same mechnism, Vera can call tests written
in Verilog or C as well.

Everycase is different and this might not address your
environment. If so, please feel free to us at
vera-support@synopsys.com. Thanks!