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dd-mj
Newbie
Joined: Jul 21, 2004
Posts: 2
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 Posted: Wed Jul 21, 2004 12:27 pm Post subject: Looking for Verilog/VHDL Documentation Extraction tool |
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I am looking for a tool like Doxygen for extracting design implementation information directly from my Verilog and VHDL code.
Design documentation is a time suck and most of the time the design docs are not in sync with the actual design, so i would like to simply extract the docs from the design.
Any ideas here? |
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EdA
Senior
Joined: Jan 06, 2004
Posts: 64
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cabriggs
Senior
Joined: Jan 12, 2004
Posts: 96
Location: Massachusetts
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| Posted: Thu Jul 22, 2004 9:31 am Post subject: Re: Looking for Verilog/VHDL Documentation Extraction tool |
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Our software group uses doc++ - http://docpp.sourceforge.net/. It seems pretty simple to use.
-cb |
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dd-mj
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Joined: Jul 21, 2004
Posts: 2
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| Posted: Thu Jul 22, 2004 11:48 am Post subject: |
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Thanks for the reply, but maybe I was not clear. I know all about the doxygen links and we are using doxygen for our C/C++/SystemC code.
I am looking for a tool to extract docs from Verilog and VHDL.
Any other ideas? |
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cabriggs
Senior
Joined: Jan 12, 2004
Posts: 96
Location: Massachusetts
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| Posted: Thu Jul 22, 2004 3:47 pm Post subject: |
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| dd-mj wrote: | Thanks for the reply, but maybe I was not clear. I know all about the doxygen links and we are using doxygen for our C/C++/SystemC code.
I am looking for a tool to extract docs from Verilog and VHDL.
Any other ideas? |
I believe the tools Ed and I mentioned will actually work with any language that supports the /* */ comment style. At least in the case of doc++, the tool simply looks for certain comment pragmas and therefore should work with Verilog.
-cb |
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RCIngham
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Joined: Feb 19, 2004
Posts: 194
Location: England (UK)
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| Posted: Mon Jul 26, 2004 3:03 am Post subject: |
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VHDL is VHSIC Hardware Description Language, and was originally meant for documenting large ASICs. It only became a simulation and synthesis source language later. Only 2 problems:
1. Many people write VHDL which is difficult to follow, due to poor choice of signal/process/component/etc. names among other reasons.
2. There are managers and others who can't read VHDL.
It is possible to write VHDL that is virtually self-documenting, but - partly because of timescale pressures and poor standards/training - this is seldom achieved. |
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vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1238
Location: Los Angeles, CA
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| Posted: Mon Jul 26, 2004 10:50 am Post subject: |
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| Quote: | | It is possible to write VHDL that is virtually self-documenting, ... |
I recommend one level higher than HDL, and that is the use of assertions to express the design intent and requirements. PSL or SystemVerilog Assertion is highly readable, but yoet not only provide good documentation, but those languages represent an "executable documentation" that does catch errors in both simulation and formal verification.
Ben Cohen
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
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Andreas
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Joined: Mar 19, 2004
Posts: 1
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RCIngham
Senior
Joined: Feb 19, 2004
Posts: 194
Location: England (UK)
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| Posted: Thu Aug 05, 2004 2:53 am Post subject: |
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| vhdlcohen wrote: |
I recommend one level higher than HDL, and that is the use of assertions to express the design intent and requirements. |
VHDL assertions good.
SystemVerilog assertions better. |
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vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1238
Location: Los Angeles, CA
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| Posted: Thu Aug 05, 2004 12:55 pm Post subject: |
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| Quote: | VHDL assertions good.
SystemVerilog assertions better. |
VHDL and SystemVerilog Assertions are 2 different beasts, as VHDL does not support assertions of temporal properties.
You probably meant to say
| Quote: | PSL with VHDL assertions good.
SystemVerilog assertions better. |
The two Accellera standards PSL and SV with SVA both support Assertion-Based Verification, however, they each serve different users.
PSL serves the communitty that uses VHDL, Verilog and is compatible with SystemVerilog (even though tools my not support that last one yet).
SVA only works with SystemVerilog because it is an integral part of SV. SVA uses SV methods, and the assertion timing is well defined in the SV cycle timing evaluation.
Which is "better"? That is really a matter of definition because there are several factors that influence the "better". These include:
- Language of preference (VHDL, Verilog, SystemVerilog)
- Tool support, availability, cost, training
- Legacy code
- Language Training
On a personal level, I feel comfortable with both PSL and SVA, as I wrote 2 books on PSL, and am currently writing a similar book on SVA to be published in beginning of 4th quarter 04. However, I don't like to use the word "better" because there are several issues to consider. BTW, VHDL200x is using PSL for its assertion language.
Ben Cohen
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
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