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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 53 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Random Generation in Verilog          Verification Guild Forum Index -> Simulation View previous topic :: View next topic   Author Message spauls Junior Joined: Apr 07, 2004 Posts: 5 Posted: Wed Apr 07, 2004 8:33 am    Post subject: Random Generation in Verilog What is the difference between $dist_uniform and $random in verilog for generation of random numbers. Back to top alexg Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa Posted: Wed Apr 07, 2004 3:22 pm    Post subject: It seems like there is no difference in disrtibution. $dist_uniform(seed, min, max) is similar to : min + {$random(seed)}%(max-min+1) For both functions, distribution is uniform. "Similar" means that both functions follows the same distribution rule, but generate different pseudo-random sequences for the same seed value. Regards, Alexander Gnusin Back to top spauls Junior Joined: Apr 07, 2004 Posts: 5 Posted: Thu Apr 08, 2004 12:39 am    Post subject: Hi , Do u have any manual or verilog book ,that describes verilog random behavior in detail regards, spauls Back to top alexg Senior Joined: Jan 07, 2004 Posts: 586 Location: Ottawa Posted: Thu Apr 08, 2004 1:52 pm    Post subject: The following link: http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Verilog/LRM/HTML/14/ch14.a.htm#42294 describes some of these functions in a more detail. Regards, Alexander Gnusin Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Simulation All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You can post new topics in this forum You can reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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