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    Verification Guild :: View topic - Dynamically starting new "processes" in VHDL
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    Dynamically starting new "processes" in VHDL

     
    This forum is locked: you cannot post, reply to, or edit topics.   This topic is locked: you cannot edit posts or make replies.    Verification Guild Forum Index -> Assertions
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    espent
    Junior
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    Joined: Mar 11, 2004
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    PostPosted: Tue Apr 06, 2004 9:25 am    Post subject: Dynamically starting new "processes" in VHDL Reply with quote

    I want to make general VHDL procedures for checking certain signal relations (a bit like dynamic ABV, e.g. continuously checking a given relation between two signals). This is no problem if the "assertions" are time-limited and sequential - or if dedicated processes are made for each simultaneous assertion - and potentially controlled via procedure calls. But - is it possible in VHDL to make dynamic parallel assertions (like a "dynamic fork") - not knowing up front how many assertions will be made? E.g. basing a general simulation environment upon assertion-procedures in a package and a testbench template, and then call any number of the predefined assertions from within the testcase driver.
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    vhdlcohen
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    Joined: Jan 05, 2004
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    Location: Los Angeles, CA

    PostPosted: Tue Apr 06, 2004 1:22 pm    Post subject: Reply with quote

    Quote:
    I want to make general VHDL procedures for checking certain signal relations (a bit like dynamic ABV, e.g. continuously checking a given relation between two signals). This is no problem if the "assertions" are time-limited and sequential - or if dedicated processes are made for each simultaneous assertion - and potentially controlled via procedure calls. But - is it possible in VHDL to make dynamic parallel assertions (like a "dynamic fork") - not knowing up front how many assertions will be made? E.g. basing a general simulation environment upon assertion-procedures in a package and a testbench template, and then call any number of the predefined assertions from within the testcase driver.

    I am not clear on the question, however I'll attempt to answer it.
    As you know, procedures can be sequential or concurrent.
    Processes must be elaborated priori to simulation, thus no dynamic creation of processes. Procedures can be called from within processes.

    concurrent procedures must also be elaborated and defined prior to simulation. The use of the "generate" statement can configure any number of concurrent procedures, but once elaborated, they are static.

    PSL, on the other hand. has the notion of current threads, thus you could have multiple sequences being checked separately. My question to you is: what specific problem are you addressing. Can you give simple examples?
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    * SystemVerilog Assertions Handbook, 3rd Edition, 2013
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    espent
    Junior
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    Joined: Mar 11, 2004
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    PostPosted: Wed Apr 07, 2004 4:22 am    Post subject: Reply with quote

    The general idea is to build an advanced general verification-environment in VHDL - to be used across multiple FPGA design-groups (in different companies). Many FPGA designers still write rather unstructured or inefficient testbenches - for various reasons. It is not an alternative for them to buy new, expensive tools like Specman or VERA nor any PSL or advanced Assertion Based tools. They do however have a huge potential for efficiency improvement through more structured internal verification reuse and a pre-qualified testbench environment.
    Then to my question: Assuming I have a master testcase process (driver) from which I can call assertion-procedures as needed, then for any time-consuming assertion the master process cannot continue until after the assertion procedure is completed. Hence this approach does not allow simultaneous assertions or assertions carried out in parallel with the testcase driver process. Alternative approaches are separate processes or entities for each assertion and duplicates for potential simultaneous "calls" of the same assertion. A 'fork' would probably have solved the problem, but this doesn't exist in VHDL. My question is: Is there anyway around this problem ? Are there any good (or good enough) work-arounds ?
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    bdeadman
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    PostPosted: Wed Apr 07, 2004 10:23 am    Post subject: Reply with quote

    I wonder if you're trying to make the task more complex than you need. It's true that PSL is specified to described an infinite number of concurrent instances of a property, in part because of it's Formal legacy, however the reality is the hardware you're verifying doesn't require an unlimited number of instances. Consider an assertion that verifies some feature of a split/postponed write - in practice the design will only be able to support a finite number of concurrent such operations so that's the number of concurrent assertions you need to support. Taking this further, if the design can only support 16 such operations and you try to create a 17th instance, it's actually an indication that something is wrong.

    My recommendation would be to consider properties as FSM's, and create the state variable(s) as arrays. You can then assign the next available array element when you want to create a new assertion instance, and you evaluate all valid array elements every time the clock 'ticks'. It's going to be awkward in VHDL but will work.

    On a more general note, another approach you might consider would be to connect the SystemC Verification extensions to VDHL. This would give you most of the features you require, without the need for additional licenses. I don't know which simulator you're using though I believe the major offerings from Cadence, Synopsys and Model Tech. all allow direct connection of SystemC in their latest incarnations, while it's also possible to connect the OSCI simulator kernel via PLI/FMI etc. calls though some work is required.

    An added advantage of the latter approach is you can implement the assertions dynamically in the SystemC domain without having to worry about the array assignment issues, though I have to wonder about the real value of doing all this now that the simulator vendors are adding native support for assertions.

    Hope this helps,

    Bernard
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    espent
    Junior
    Junior


    Joined: Mar 11, 2004
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    PostPosted: Tue Apr 13, 2004 2:16 am    Post subject: Reply with quote

    Yes, - this attempted approach is definitely complex - and maybe too complex. The idea was to handle this once, and then provide a very simple to use, reusable verification environment - allowing some sort of dynamic concurrent assertions with intuitive procedure calls.
    For someone who knows VHDL and verification very well this will probably not make much sense, but my experience is that many FPGA designers still write "RTL-like" testbenches (not the typical Verification Guild reader Wink.
    SystemC would thus not be a feasible option, due both to the complexity compared to VHDL/RTL and to the compilation support. Unfortunately the new tool-versions, supporting more advanced assertions, will probably be in the upper price range.
    I will have a look at your idea with FSMs/arrays to see if this can be used as a feasible workaround.
    Thanks for your help.
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