Verifying Verilog Fixed Point Designs with Matlab

finbarr · Newbie Joined: Jan 24, 2004 Posts: 1

Hi,

I have an interesting problem (and solution) and I'm wondering has this been considered before...?

The scenario:
I am developing low power adaptive DSP algorithms in MATLAB.
MATLAB works with floating point variables.

I use verilog (Synopsys' VCS simulator) to implement the algorithms in fixed point arithmetic.

The problem:
The simulator waveform shows me busses (of various widths) which represent fixed point numbers. The fixed point numbers may have different radix points.

So I may have two sixteen bit fixed point numbers which have the same binary representation but different value (depending on the position of the radix point).

I want to be able to look quickly at any signal (from the verilog simulation) in MATLAB and it be scaled to the correct value.

The solution:
I dump the binary of all signals of interest to me into a text dump file (using the verilog $monitorb sysytem task).

The signals of interest are first identified in a file (with their radix positions)
and then this file is processed before the verilog simulation by a PERL script which automatically generates a verilog include file and a MATLAB post processing script.

I then post process the verilog dump file using a C program which is linked to and MATLAB application Programming interface (called MEX).

------
And just in case you haven't followed all of that.... here's a synopsis...

text_file of signals processed by PERL script to create
* UNIX run script
* MATLAB post processing script
* Verilog monitor file

The verilog simulation is run... to create a verilog dump file...

then a MEX/C program processes the output of the verilog simulation which allows signals to be viewed in MATLAB.

So what?

* I can make this available to anyone who is having similar issues...
You have to know (or at least not be daunted by) verilog,C,perl, MEX and
MATLAB to use it...
* I expect that this is a solved problem. I wonder have I overcomplicated it.
Anyone who has developed DSP algorithms in C or MATLAB will be aware
of this issue.

Any thoughts or ideas are welcome.

Regards,

Finbarr

grouby · Newbie Joined: Jan 12, 2004 Posts: 1

Here are some ideas ...

Algotithm Design

Are you developping your algorithms in MATLAB or SIMULINK ?
- MATLAB : you can use the quantization toolbox to investigate fixed-point implementations
- SIMULINK : you can use the fixed-point features of the DSP Blockset to investigate fixed-point implementations

Code Generation

Mathworks is supposed to release a VHDL code generator for fixed-point SIMULINK designs. I don't know about Verilog code generation (maybe in subsequent releases ?).
XILINX and ALTERA already have proprietary solutions but I expect that the Mathworks code generator will not be vendor dependent.

Data Visualization

You could write a MATLAB script which imports data from a VCD formal file.
Of course, this requires knowledge of the VCD file format.
This would be a cool user contribution.

tomahawkins · Senior Joined: Mar 23, 2004 Posts: 29

Here's a trick...

1. Convert your RTL to C++ with Verilator (I'm assuming Verilog).
2. Write a wrapper around the Verilated RTL to match the Simulink API.
3. Compile with mex.
4. Import into Simulink via sfunctions.

Now you can co-simulate your RTL with Simulink. Once you have the flow setup, you'll find simulating RTL with Simulink is surprisingly useful.