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Verification Guild: Forums

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Moderator: Janick Bergeron

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No new posts Announcement: Be aware of CONFIDENTIAL and PROPRIETARY information!
0 Janick 11122 Tue Feb 19, 2008 10:15 am
Janick View latest post
No new posts get_seed()
4 gure 2553 Mon Dec 05, 2005 11:58 am
5S63 View latest post
No new posts Verification Census: Discussions
7 vhdlcohen 5965 Sun Dec 04, 2005 11:47 pm
Boone View latest post
No new posts please help with nc-simulator
6 andyquan 3422 Sat Dec 03, 2005 11:36 pm
andyquan View latest post
No new posts SVA for I2C
14 dudeeg 6057 Fri Dec 02, 2005 12:45 pm
vhdlcohen View latest post
No new posts Enumerated variable initialization in SV
2 supertrooper 1579 Wed Nov 30, 2005 6:27 pm
dave_59 View latest post
No new posts RVM Bus functional models: logical -> physical conversion
3 Boone 2048 Wed Nov 30, 2005 10:23 am
Janick View latest post
No new posts What was the hardest thing to verify?
11 Adam 7242 Tue Nov 29, 2005 10:54 pm
alain94040 View latest post
No new posts Specman, VCS MX, VHDL top and Verilog underneath
4 jwatt 6080 Tue Nov 29, 2005 1:34 pm
jwatt View latest post
No new posts cover property;???
1 kirloy 1563 Mon Nov 28, 2005 12:25 pm
vhdlcohen View latest post
No new posts A question about specman & vera
11 claymore 8325 Sun Nov 27, 2005 10:47 am
aelms View latest post
No new posts NTB compile problems with OpenVera
1 IanK 1845 Wed Nov 23, 2005 1:28 pm
Martin1234 View latest post
No new posts Vera functional coverage HTML reports not HTML compliant
5 Martin1234 3339 Tue Nov 22, 2005 11:43 am
nall View latest post
No new posts PSL: math - NOT_OP, never - outside of simple subset
0 kirloy 1259 Thu Nov 17, 2005 6:37 am
kirloy View latest post
No new posts No Glory (or Money) in Verification
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28 I_Regress 15030 Mon Nov 14, 2005 8:37 pm
BitterSpock View latest post
No new posts [SOLVED] NTB: stands for "Needs Tera Bytes"?
7 Martin1234 4237 Mon Nov 14, 2005 8:16 pm
BitterSpock View latest post
No new posts Change X propagation in Verilog sim
4 webb4789 3697 Sun Nov 13, 2005 11:11 pm
alexg View latest post
No new posts Changing clock frequency in VHDL
12 Vazquez 3294 Fri Nov 11, 2005 6:28 pm
Janick View latest post
No new posts PSL or SVA? That is the question!
7 vhdlcohen 2467 Fri Nov 11, 2005 4:51 pm
vhdlcohen View latest post
No new posts Eliminating time-zero race on module inputs
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19 BitterSpock 6597 Fri Nov 11, 2005 4:05 pm
cliffc View latest post
No new posts Vera class task callable without instance!
4 Martin1234 1583 Fri Nov 11, 2005 10:14 am
richardbradley View latest post
No new posts Embedded Verification Language (was: Dream Hardware Veri...)
2 tomahawkins 2420 Tue Nov 08, 2005 7:15 pm
mpatil View latest post
No new posts write verification ip use openvera
2 holly 1651 Mon Nov 07, 2005 9:10 pm
Arnold View latest post
No new posts HDCaml
0 tomahawkins 1593 Sun Nov 06, 2005 1:09 pm
tomahawkins View latest post
No new posts "post-observed" region in systemverilog
2 nasim 1777 Sat Nov 05, 2005 6:19 pm
dave_59 View latest post
No new posts Implementing VMM when you have processors in your SOC
6 BitterSpock 2968 Fri Nov 04, 2005 10:56 am
BitterSpock View latest post
No new posts Dream Hardware Verification Language
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34 mpatil 10941 Tue Nov 01, 2005 10:48 pm
z View latest post
No new posts Verification of a Microprocessor
2 Arthur 1921 Tue Nov 01, 2005 4:59 pm
BitterSpock View latest post
No new posts IEEE HLDVT Workshop Registration and Advance Program
0 harrydfoster 1427 Sat Oct 29, 2005 4:04 pm
harrydfoster View latest post
No new posts Space Hardware testbenching in VHDL
1 waxman 1503 Wed Oct 26, 2005 4:11 pm
vhdlcohen View latest post
No new posts Gate Simulations
7 kartik_n 8292 Tue Oct 25, 2005 1:59 pm
croussel View latest post
No new posts Functional Coverage and VMM
2 Simon 1603 Tue Oct 25, 2005 7:49 am
Simon View latest post
No new posts Opinions about Avery VIP?
0 daveread 1256 Fri Oct 21, 2005 4:48 pm
daveread View latest post
No new posts Starting Timing simulation with do-file
3 Vazquez 3651 Fri Oct 21, 2005 2:28 am
Vazquez View latest post
No new posts e language applications
3 kumarshri 2146 Fri Oct 14, 2005 11:06 am
snwuxing View latest post
No new posts ASIC address decoding verification
13 sampsont 5485 Fri Oct 14, 2005 10:53 am
richardbradley View latest post
No new posts Pragmas in Cadence's Incisive *Integrated* Code Coverage?
2 PoldiX 2878 Wed Oct 12, 2005 4:43 am
PoldiX View latest post
No new posts verification complexity theory?
9 confused 4281 Tue Oct 11, 2005 4:33 pm
mpatil View latest post
No new posts SystemVerilog constraints
3 romi 4964 Tue Oct 11, 2005 10:09 am
vhdlcohen View latest post
No new posts PSL: meaning of always
6 teru 3066 Mon Oct 10, 2005 10:11 am
cindy View latest post
No new posts DVCon'05 Questionnaire results
5 vhdlcohen 2900 Tue Oct 04, 2005 11:45 pm
alexg View latest post
No new posts What makes a good verification engineer?
8 Adam 5204 Tue Oct 04, 2005 3:42 pm
Adam View latest post
No new posts rvm_log verbosity setting from the command line?
2 kev 1604 Fri Sep 30, 2005 3:13 am
kev View latest post
No new posts typedef error in vera
0 vidiraj 1364 Thu Sep 29, 2005 4:24 am
vidiraj View latest post
No new posts Transaction based testbench: encapsulating the client calls?
8 AndrewFPGA 4032 Wed Sep 28, 2005 11:36 pm
Janick View latest post
No new posts SystemVerilog Functions vs. string methods
1 Izmunuti 2890 Tue Sep 27, 2005 9:48 am
dave_59 View latest post
No new posts Guidelines on use of SV import of packages
0 vhdlcohen 1268 Fri Sep 23, 2005 7:42 pm
vhdlcohen View latest post
No new posts How to get current object name in Vera ?
3 senswi 2162 Fri Sep 23, 2005 5:28 pm
mbowler View latest post
No new posts PSL: referencing to block item
1 kirloy 1126 Fri Sep 23, 2005 12:28 pm
srini View latest post
No new posts compiling VCS ntb code
6 kev 2673 Tue Sep 20, 2005 11:59 am
kev View latest post
No new posts parameters for a scope
1 guruje 1545 Sun Sep 18, 2005 7:29 pm
chrisspear View latest post
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