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| Most Popular - Top 25 | Show Top: [ 10 - 25 - 50 | 1% - 5% - 10% ]
|  Random Number Generator 
Description: Random number generator package
Version: Filesize: 32 bytes
Added on: 14-Dec-2003 Downloads: 12394
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Category: Utilities/VHDL
Directed Verification Plan
Description: Outline of a verification plan using a directed test strategy
Version: Filesize: 52 bytes
Added on: 14-Dec-2003 Downloads: 9754
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Category: Methodology/Methodology
Verilog & VHDL behavioral models
Description: Pin-accurate behavioral (i.e. non-synthesizable) models in Verilog and VHDL (zip)
Version: Filesize: 55 bytes
Added on: 14-Dec-2003 Downloads: 6702
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Category: Verification Guild Project/Verification Guild Project
Functional Specification
Description: Functional specification of a 4-port user-to-network ATM switch node (PDF)
Version: Filesize: 85 bytes
Added on: 14-Dec-2003 Downloads: 5575
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Category: Verification Guild Project/Verification Guild Project
Random Number Generator
Description: Random number generator package
Version: Filesize: 28 bytes
Added on: 14-Dec-2003 Downloads: 5462
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Category: Utilities/VHDL
HEC computation C program
Description: Reference C program for the correct computation of an ATM cell HEC value
Version: Filesize: 2 bytes
Added on: 14-Dec-2003 Downloads: 2570
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Category: Verification Guild Project/Verification Guild Project
parallel
Description: Parallel is a distributed batch process controller. It is written to allow you to run an arbitrary number of regression tests across any number of (Li/U)nix machines. It uses no deamon of its own, but instead relies on NFS, and either ssh or rsh to communicate with remote machines.
Version: 1.0 Filesize: 27.50 Kb
Added on: 14-Feb-2004 Downloads: 2376
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Category: Utilities/Utilities
vera.vim
Description: VIM syntax rules for Vera
Version: 5.0 Filesize: 0 bytes
Added on: 14-Dec-2003 Downloads: 2372
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Category: Utilities/Vera
Region class for SystemVerilog
Description: Region class for use with SystemVerilog
INTRODUCTION:
The OpenVera region is not supported in SystemVerilog, so this class
is provided as a substitute. Compile this class along with the rest
of the testbench.
INITIALIZATION:
The following code creates a single region:
int regionID;
regionID = alloc(REGION, 0, 1);
The equivalent code in SystemVerilog is:
Region regionID;
regionID = new(); // No name given
A name can be passed to new() for use in the display task.
USAGE:
Use a region to reserve a value, blocking if in use:
region_enter(WAIT, regionID, value); // Vera
and
regionID.region_enter(Region::WAIT, value); // SystemVerilog
Use a region to reserve a value, checking status:
status = region_enter(NO_WAIT, regionID, value); // Vera
and
regionID.region_enter(Region::NO_WAIT, value); // SystemVerilog
Leave a region:
region_exit(regionID, value); // Vera
and
regionID.region_exit(value); // SystemVerilog
Display the currently reserved value:
regionID.display(); // Only in SystemVerilog
Version: Filesize: 0 bytes
Added on: 27-Feb-2006 Downloads: 2349
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Category: Utilities/SystemVerilog
vrhfix
Description: Fix header files generated using the -h command-line option
Version: 1.4 Filesize: 6 bytes
Added on: 14-Dec-2003 Downloads: 1413
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Category: Utilities/Vera
RegWorks(TM) Spec2Reg
Description: The RegWorks(TM) is a set of tools intended to automate the process of register class creation directly from the design specification. It can also be used with other third party tools such as Synopsys RAL or equivalent.
Version: 1.0 Filesize: 32 bytes
Added on: 16-Nov-2009 Downloads: 986
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Category: Utilities/SystemVerilog
VPP
Description: Verilog pre-processor
Version: 1.2 Filesize: 39.06 Kb
Added on: 19-Mar-2009 Downloads: 903
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Category: Utilities/Verilog
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